A built-in self-repair scheme for NOR-type flash memory

Yu Ying Hsiao, Chao Hsun Chen, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)


The strong demand of non-volatile memory for SOC and SIP applications has made flash memory increasingly important. However, deep submicron defects and process uncertainties are causing yield loss of memory products. To solve the yield issue, built-in self-repair (BISR) is widely believed to be cost effective. It is, however, non-trivial to implement BISR on flash memories. In this paper we propose a BISR scheme for NOR-type flash memory. The BISR scheme performs built-in self-test (BIST), built-in redundancy analysis (BIRA), as well as on-chip repair. A typical redundancy architecture for NOR-type flash memory is assumed, based on which we present a redundancy analysis (RA) algorithm. Experimental result shows that the proposed BISR scheme can effectively repair most defective memories.

Original languageEnglish
Title of host publicationProceedings - 24th IEEE VLSI Test Symposium
Number of pages6
Publication statusPublished - 2006 Nov 22
Event24th IEEE VLSI Test Symposium - Berkeley, CA, United States
Duration: 2006 Apr 302006 May 4

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Other24th IEEE VLSI Test Symposium
Country/TerritoryUnited States
CityBerkeley, CA

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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