A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters

Chih Wea Wang, Ruey Shing Tzeng, Chi Feng Wu, Chih Tsun Huang, Cheng Wen Wu, Shi Yu Huang, Shyh Horng Lin, Hsin Po Wang

Research output: Contribution to journalConference article

16 Citations (Scopus)

Abstract

Testing and diagnosis are important issues in system-on-chip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a built-in self-test (BIST) and self-diagnosis (BISD) scheme for embedded SRAMs, suitable for SOC applications. It supports manufacturing test as well as diagnosis for design verification and yield improvement. With low hardware cost, our memory BISD approach can handle various types of SRAM, including pipelined, multi-port, and multi-clock architectures. In addition, a test scheduling methodology and a BISD compiler are also implemented, which reduce the testing time as well as test development time.

Original languageEnglish
Pages (from-to)103-108
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 2001 Dec 1
EventProceedings of the 10th Asian Test Symposium - Kyoto, Japan
Duration: 2001 Nov 192001 Nov 21

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Built-in self test
Static random access storage
Testing
Computer hardware
Clocks
Scheduling
Data storage equipment
Costs

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Wang, C. W., Tzeng, R. S., Wu, C. F., Huang, C. T., Wu, C. W., Huang, S. Y., ... Wang, H. P. (2001). A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters. Proceedings of the Asian Test Symposium, 103-108.
Wang, Chih Wea ; Tzeng, Ruey Shing ; Wu, Chi Feng ; Huang, Chih Tsun ; Wu, Cheng Wen ; Huang, Shi Yu ; Lin, Shyh Horng ; Wang, Hsin Po. / A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters. In: Proceedings of the Asian Test Symposium. 2001 ; pp. 103-108.
@article{e765fb8445b84886862fa545d0c73f6a,
title = "A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters",
abstract = "Testing and diagnosis are important issues in system-on-chip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a built-in self-test (BIST) and self-diagnosis (BISD) scheme for embedded SRAMs, suitable for SOC applications. It supports manufacturing test as well as diagnosis for design verification and yield improvement. With low hardware cost, our memory BISD approach can handle various types of SRAM, including pipelined, multi-port, and multi-clock architectures. In addition, a test scheduling methodology and a BISD compiler are also implemented, which reduce the testing time as well as test development time.",
author = "Wang, {Chih Wea} and Tzeng, {Ruey Shing} and Wu, {Chi Feng} and Huang, {Chih Tsun} and Wu, {Cheng Wen} and Huang, {Shi Yu} and Lin, {Shyh Horng} and Wang, {Hsin Po}",
year = "2001",
month = "12",
day = "1",
language = "English",
pages = "103--108",
journal = "Proceedings of the Asian Test Symposium",
issn = "1081-7735",
publisher = "IEEE Computer Society",

}

Wang, CW, Tzeng, RS, Wu, CF, Huang, CT, Wu, CW, Huang, SY, Lin, SH & Wang, HP 2001, 'A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters', Proceedings of the Asian Test Symposium, pp. 103-108.

A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters. / Wang, Chih Wea; Tzeng, Ruey Shing; Wu, Chi Feng; Huang, Chih Tsun; Wu, Cheng Wen; Huang, Shi Yu; Lin, Shyh Horng; Wang, Hsin Po.

In: Proceedings of the Asian Test Symposium, 01.12.2001, p. 103-108.

Research output: Contribution to journalConference article

TY - JOUR

T1 - A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters

AU - Wang, Chih Wea

AU - Tzeng, Ruey Shing

AU - Wu, Chi Feng

AU - Huang, Chih Tsun

AU - Wu, Cheng Wen

AU - Huang, Shi Yu

AU - Lin, Shyh Horng

AU - Wang, Hsin Po

PY - 2001/12/1

Y1 - 2001/12/1

N2 - Testing and diagnosis are important issues in system-on-chip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a built-in self-test (BIST) and self-diagnosis (BISD) scheme for embedded SRAMs, suitable for SOC applications. It supports manufacturing test as well as diagnosis for design verification and yield improvement. With low hardware cost, our memory BISD approach can handle various types of SRAM, including pipelined, multi-port, and multi-clock architectures. In addition, a test scheduling methodology and a BISD compiler are also implemented, which reduce the testing time as well as test development time.

AB - Testing and diagnosis are important issues in system-on-chip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a built-in self-test (BIST) and self-diagnosis (BISD) scheme for embedded SRAMs, suitable for SOC applications. It supports manufacturing test as well as diagnosis for design verification and yield improvement. With low hardware cost, our memory BISD approach can handle various types of SRAM, including pipelined, multi-port, and multi-clock architectures. In addition, a test scheduling methodology and a BISD compiler are also implemented, which reduce the testing time as well as test development time.

UR - http://www.scopus.com/inward/record.url?scp=0035701267&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035701267&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0035701267

SP - 103

EP - 108

JO - Proceedings of the Asian Test Symposium

JF - Proceedings of the Asian Test Symposium

SN - 1081-7735

ER -