A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters

Chih Wea Wang, Ruey Shing Tzeng, Chi Feng Wu, Chih Tsun Huang, Cheng Wen Wu, Shi Yu Huang, Shyh Horng Lin, Hsin Po Wang

Research output: Contribution to journalConference articlepeer-review

17 Citations (Scopus)


Testing and diagnosis are important issues in system-on-chip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a built-in self-test (BIST) and self-diagnosis (BISD) scheme for embedded SRAMs, suitable for SOC applications. It supports manufacturing test as well as diagnosis for design verification and yield improvement. With low hardware cost, our memory BISD approach can handle various types of SRAM, including pipelined, multi-port, and multi-clock architectures. In addition, a test scheduling methodology and a BISD compiler are also implemented, which reduce the testing time as well as test development time.

Original languageEnglish
Pages (from-to)103-108
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 2001 Dec 1
EventProceedings of the 10th Asian Test Symposium - Kyoto, Japan
Duration: 2001 Nov 192001 Nov 21

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


Dive into the research topics of 'A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters'. Together they form a unique fingerprint.

Cite this