A built-in self-test scheme for 3D RAMs

Yun Chao Yu, Che Wei Chou, Jin Fu Li, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Three-dimensional (3D) random access memory (RAM) using through-silicon vias for inter-die interconnects has been considered as a new approach to overcome the memory wall. In this paper, we propose a built-in self-test (BIST) scheme for 3D RAMs. In the BIST scheme, a clock-domain-crossing-aware test pattern generator is proposed to cope with the clock-domain-crossing issue. An inter-die synchronization mechanism is also proposed to synchronize the BIST circuits in different dies. Furthermore, the BIST circuit provides the high-programmability feature to support the selection of RAMs in a die for testing such that it can support thermal management during the test. We design the proposed BIST scheme in a 3D IC with processor and RAM dies. Experimental results show that the area cost of the BIST circuit is very small. The area overhead of the BIST circuit for four 8192×64-bit RAMs in a die is only 0.45% using TSMC 90nm 1P9M CMOS process technology.

Original languageEnglish
Title of host publicationITC 2012 - International Test Conference 2012, Proceedings
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 International Test Conference, ITC 2012 - Anaheim, CA, United States
Duration: 2012 Nov 62012 Nov 8

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Conference

Conference2012 International Test Conference, ITC 2012
CountryUnited States
CityAnaheim, CA
Period12-11-0612-11-08

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

Fingerprint Dive into the research topics of 'A built-in self-test scheme for 3D RAMs'. Together they form a unique fingerprint.

Cite this