A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit

Meng Chi Chen, Tsung Hsuan Wu, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)


FinFET is a feasible solution to short-channel effects that has been encountered by planar transistors during process scaling, and is widely adopted in advanced CMOS technologies. However, the special physical structure of FinFET also brings new defect models, which are hard to detect by conventional March algorithms, thus a more effective test methodology is required. In this paper, we investigate defect candidates in a FinFET 6T-SRAM circuit, analyze their fault behaviors, and propose a built-in self-test (BIST) scheme to enhance fault coverage and reduce test time. The proposed BIST approach is able to detect all target defects with only one read cycle, which reduces the required test algorithm complexity and hence reduces test time. This BIST scheme can be used with classical March algorithms, such as the March C-, to extend fault coverage beyond static single cell or coupling faults, thus reducing the defect level.

Original languageEnglish
Title of host publicationProceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)9781538694664
Publication statusPublished - 2018 Dec 6
Event27th IEEE Asian Test Symposium, ATS 2018 - Hefei, China
Duration: 2018 Oct 152018 Oct 18

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Other27th IEEE Asian Test Symposium, ATS 2018

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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