TY - GEN
T1 - A built-in self-test scheme for the post-bond test of TSVs in 3D ICs
AU - Huang, Yu Jen
AU - Li, Jin Fu
AU - Chen, Ji Jan
AU - Kwai, Ding Ming
AU - Chou, Yung Fa
AU - Wu, Cheng Wen
PY - 2011/7/1
Y1 - 2011/7/1
N2 - Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18m CMOS technology for a 1632 TSV array in which each TSV cell size is 45m2 is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.
AB - Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18m CMOS technology for a 1632 TSV array in which each TSV cell size is 45m2 is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.
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U2 - 10.1109/VTS.2011.5783749
DO - 10.1109/VTS.2011.5783749
M3 - Conference contribution
AN - SCOPUS:79959674608
SN - 9781612846552
T3 - Proceedings of the IEEE VLSI Test Symposium
SP - 20
EP - 25
BT - Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011
T2 - 2011 29th IEEE VLSI Test Symposium, VTS 2011
Y2 - 1 May 2011 through 5 May 2011
ER -