This article presents a 14-b 100-MS/s single-channel pipelined-successive-approximation register (SAR) ADC using a weighted-averaging correlated level shifting (WACLS) technique. For a closed-loop residue amplification, the error voltage due to the finite operational amplifier (opamp) gain can be ideally removed by the proposed WACLS technique with a low-gain opamp. In addition, the opamp bandwidth degradation, by an extra level-shift capacitor (CLS) in two-phase amplification CLS-based circuits, can be relaxed and minimized in WACLS. Furthermore, a speed-enhancement scheme is provided to alleviate the speed degradation owing to one extra amplification phase and long bit-cycling time from two-phase amplification and SAR circuits, respectively. A modified reference swapping (RS) technique is applied to diminish the capacitor mismatch error without any calibration. A quick startup ring amplifier design is introduced for duty-cycled control power saving. The chip is implemented in the 28-nm CMOS technology and occupies an active area of 0.018 mm2. At 100 MS/s and Nyquist-rate input, the measured SNDR is 71.7 dB with 0.7-mW power consumption only. The calibration-free ADC achieves Walden and Schreier figure-of-merit of 2.2 fJ/conversion-step and 180.2 dB, respectively. Compared with the prior-art ADCs with sampling frequency > 100 MS/s and SNDR > 65 dB, this work advances the state-of-the-art by 3 × and 5.3 dB, respectively.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering