A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM

Jiyue Yang; Di Wu; Albert Lee; Seyed Armin Razavi; Puneet Gupta; Kang L. Wang; Sudhakar Pamarti

doi:10.1109/ESSDERC53440.2021.9631784

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM

Jiyue Yang, Di Wu, Albert Lee, Seyed Armin Razavi, Puneet Gupta, Kang L. Wang, Sudhakar Pamarti

College of Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this paper, we propose an in-memory True Random Number Generator (TRNG) using Voltage-Controlled MRAM that doesn't require calibration of the writing pulse's width and amplitude. Previous solution using Spin Transfer Torque (STT) MRAM requires calibration for every MTJ, thus making the multi-row random number generation inside the memory impossible. We also propose a 100% relative throughput digital bias correction circuit that doesn't degrade bit rate. The VC- MTJs are fabricated in CMOS BEOL compatible process with an 80 nm diameter and high TMR ratio of 160%. MRAM array circuits and bias correction circuits are fabricated in 65 nm CMOS technology and wire-bonded with the VC-MTJ devices. Multiple VC-MTJs are tested and shown to pass all NIST randomness tests.

Original language	English
Title of host publication	ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings
Publisher	Editions Frontieres
Pages	115-118
Number of pages	4
ISBN (Electronic)	9781665437479
DOIs	https://doi.org/10.1109/ESSDERC53440.2021.9631784
Publication status	Published - 2021
Event	51st IEEE European Solid-State Device Research Conference, ESSDERC 2021 - Virtual, Online, France Duration: 2021 Sept 6 → 2021 Sept 9

Publication series

Name	European Solid-State Device Research Conference
Volume	2021-September
ISSN (Print)	1930-8876

Conference

Conference	51st IEEE European Solid-State Device Research Conference, ESSDERC 2021
Country/Territory	France
City	Virtual, Online
Period	21-09-06 → 21-09-09

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ESSDERC53440.2021.9631784

Cite this

Yang, J., Wu, D., Lee, A., Razavi, S. A., Gupta, P., Wang, K. L., & Pamarti, S. (2021). A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM. In ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings (pp. 115-118). (European Solid-State Device Research Conference; Vol. 2021-September). Editions Frontieres. https://doi.org/10.1109/ESSDERC53440.2021.9631784

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title = "A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM",

abstract = "In this paper, we propose an in-memory True Random Number Generator (TRNG) using Voltage-Controlled MRAM that doesn't require calibration of the writing pulse's width and amplitude. Previous solution using Spin Transfer Torque (STT) MRAM requires calibration for every MTJ, thus making the multi-row random number generation inside the memory impossible. We also propose a 100% relative throughput digital bias correction circuit that doesn't degrade bit rate. The VC- MTJs are fabricated in CMOS BEOL compatible process with an 80 nm diameter and high TMR ratio of 160%. MRAM array circuits and bias correction circuits are fabricated in 65 nm CMOS technology and wire-bonded with the VC-MTJ devices. Multiple VC-MTJs are tested and shown to pass all NIST randomness tests.",

author = "Jiyue Yang and Di Wu and Albert Lee and Razavi, {Seyed Armin} and Puneet Gupta and Wang, {Kang L.} and Sudhakar Pamarti",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 51st IEEE European Solid-State Device Research Conference, ESSDERC 2021 ; Conference date: 06-09-2021 Through 09-09-2021",

year = "2021",

doi = "10.1109/ESSDERC53440.2021.9631784",

language = "English",

series = "European Solid-State Device Research Conference",

publisher = "Editions Frontieres",

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booktitle = "ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings",

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Yang, J, Wu, D, Lee, A, Razavi, SA, Gupta, P, Wang, KL & Pamarti, S 2021, A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM. in ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings. European Solid-State Device Research Conference, vol. 2021-September, Editions Frontieres, pp. 115-118, 51st IEEE European Solid-State Device Research Conference, ESSDERC 2021, Virtual, Online, France, 21-09-06. https://doi.org/10.1109/ESSDERC53440.2021.9631784

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM. / Yang, Jiyue; Wu, Di; Lee, Albert et al.
ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings. Editions Frontieres, 2021. p. 115-118 (European Solid-State Device Research Conference; Vol. 2021-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Wang, Kang L.

AU - Pamarti, Sudhakar

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N2 - In this paper, we propose an in-memory True Random Number Generator (TRNG) using Voltage-Controlled MRAM that doesn't require calibration of the writing pulse's width and amplitude. Previous solution using Spin Transfer Torque (STT) MRAM requires calibration for every MTJ, thus making the multi-row random number generation inside the memory impossible. We also propose a 100% relative throughput digital bias correction circuit that doesn't degrade bit rate. The VC- MTJs are fabricated in CMOS BEOL compatible process with an 80 nm diameter and high TMR ratio of 160%. MRAM array circuits and bias correction circuits are fabricated in 65 nm CMOS technology and wire-bonded with the VC-MTJ devices. Multiple VC-MTJs are tested and shown to pass all NIST randomness tests.

AB - In this paper, we propose an in-memory True Random Number Generator (TRNG) using Voltage-Controlled MRAM that doesn't require calibration of the writing pulse's width and amplitude. Previous solution using Spin Transfer Torque (STT) MRAM requires calibration for every MTJ, thus making the multi-row random number generation inside the memory impossible. We also propose a 100% relative throughput digital bias correction circuit that doesn't degrade bit rate. The VC- MTJs are fabricated in CMOS BEOL compatible process with an 80 nm diameter and high TMR ratio of 160%. MRAM array circuits and bias correction circuits are fabricated in 65 nm CMOS technology and wire-bonded with the VC-MTJ devices. Multiple VC-MTJs are tested and shown to pass all NIST randomness tests.

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A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM

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