A closed-form delay formula for on-chip RLC interconnects in current-mode signaling

Mingcui Zhou, Wentai Liu, Mohanasankar Sivaprakasam

Research output: Contribution to journalConference articlepeer-review

8 Citations (Scopus)

Abstract

Current-mode signaling significantly increases the bandwidth of on-chip interconnects compared to voltage mode signaling and reduces the overall propagation delay. A delay formula (line and load delay) for current mode is necessary for estimation of delay and bandwidth for VLSI systems. The inductance effect of interconnects is more dominant in sub-micron technology. So a RC approximation results in significant error in delay estimation. This paper presents a closed-form delay formula for on-chip RLC interconnects for current mode signaling. The delay formula reported herein is derived based on the modified nodal analysis (MNA) formulation and an equivalent lumped model representation of inductance effects. Compared to computationally intensive methods, this method results in a simple yet accurate expression by 'absorbing' the inductance into the RC model. The formula is verified via HSPICE simulations and is 5% accuracy over a wide range of interconnect parameters. The accuracy of the expression under different ranges of parameters is discussed, enabling this to be used as design tool.

Original languageEnglish
Article number1464780
Pages (from-to)1082-1085
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
Publication statusPublished - 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 2005 May 232005 May 26

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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