A CMOS quadrature VCO with subharmonic and injection-locked techniques

Shuenn Yuh Lee; Liang Hung Wang; Yu Heng Lin

doi:10.1109/TCSII.2010.2082990

A CMOS quadrature VCO with subharmonic and injection-locked techniques

Shuenn Yuh Lee, Liang Hung Wang, Yu Heng Lin

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

32 Citations (Scopus)

Abstract

A 1-V quadrature voltage-controlled oscillator (QVCO) using subharmonic and injection-locked techniques (SHIL-QVCO) is presented. Instead of using the traditional transformer-coupling LC tank with a large area to implement the quadrature output, we use a frequency-doubled differential pair with an injection-locked method. The proposed QVCO is implemented with a TSMC 0.18-μm 1P6M CMOS process having a 1.4 × 0.67 mm² chip area. This QVCO has the advantages of low phase noise and low power consumption. Experimental results show that the QVCO has a phase noise of -126 dBc/Hz at an offset frequency of 1 MHz and a power consumption of 4.9 mW to achieve a 186 figure of merit. Moreover, a tuning frequency between 2.17 and 2.52 GHz can be obtained with a tuning voltage range of 0-1 V for the IEEE 802.15.4.

Original language	English
Article number	5621885
Pages (from-to)	843-847
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	57
Issue number	11
DOIs	https://doi.org/10.1109/TCSII.2010.2082990
Publication status	Published - 2010 Nov

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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title = "A CMOS quadrature VCO with subharmonic and injection-locked techniques",

abstract = "A 1-V quadrature voltage-controlled oscillator (QVCO) using subharmonic and injection-locked techniques (SHIL-QVCO) is presented. Instead of using the traditional transformer-coupling LC tank with a large area to implement the quadrature output, we use a frequency-doubled differential pair with an injection-locked method. The proposed QVCO is implemented with a TSMC 0.18-μm 1P6M CMOS process having a 1.4 × 0.67 mm2 chip area. This QVCO has the advantages of low phase noise and low power consumption. Experimental results show that the QVCO has a phase noise of -126 dBc/Hz at an offset frequency of 1 MHz and a power consumption of 4.9 mW to achieve a 186 figure of merit. Moreover, a tuning frequency between 2.17 and 2.52 GHz can be obtained with a tuning voltage range of 0-1 V for the IEEE 802.15.4.",

author = "Lee, {Shuenn Yuh} and Wang, {Liang Hung} and Lin, {Yu Heng}",

note = "Funding Information: Manuscript received June 24, 2010; accepted September 13, 2010. Date of publication October 21, 2010; date of current version November 17, 2010. This work was supported in part by the Chip Implementation Center, by the Wireless Communication Laboratories (WC Lab.), and by the National Science Council, Taiwan, under Grant NSC 99-2628-E-194-032, Grant NSC 99-2220-E-194-001, and Grant NSC 99-2220-E-194-006. This paper was recommended by Associate Editor A. Liscidini.",

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N2 - A 1-V quadrature voltage-controlled oscillator (QVCO) using subharmonic and injection-locked techniques (SHIL-QVCO) is presented. Instead of using the traditional transformer-coupling LC tank with a large area to implement the quadrature output, we use a frequency-doubled differential pair with an injection-locked method. The proposed QVCO is implemented with a TSMC 0.18-μm 1P6M CMOS process having a 1.4 × 0.67 mm2 chip area. This QVCO has the advantages of low phase noise and low power consumption. Experimental results show that the QVCO has a phase noise of -126 dBc/Hz at an offset frequency of 1 MHz and a power consumption of 4.9 mW to achieve a 186 figure of merit. Moreover, a tuning frequency between 2.17 and 2.52 GHz can be obtained with a tuning voltage range of 0-1 V for the IEEE 802.15.4.

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