TY - GEN
T1 - A comparative study of fin-last and fin-first SOI FinFETs
AU - Lu, Darsen
AU - Chang, Josephine
AU - Guillorn, Michael A.
AU - Lin, Chung Hsun
AU - Johnson, Jeffrey
AU - Oldiges, Philip
AU - Rim, Ken
AU - Khare, Mukesh
AU - Haensch, Wilfried
PY - 2013
Y1 - 2013
N2 - Two FinFET fabrication processes are compared with simulation: the conventional fin-first process and the novel fin-last process. With the fin-last process, more longitudinal strain can be incorporated into the channel from source and drain SiGe stressor than fin-first. pFET mobility advantage is 15% at fully-strained condition and with silicon recess. Maintaining vertical junction uniformity is the main challenge for fin-last. However, its impact on parasitic resistance and capacitances are small. Vertical junction non-uniformity is improved with source and drain recess and doping optimization.
AB - Two FinFET fabrication processes are compared with simulation: the conventional fin-first process and the novel fin-last process. With the fin-last process, more longitudinal strain can be incorporated into the channel from source and drain SiGe stressor than fin-first. pFET mobility advantage is 15% at fully-strained condition and with silicon recess. Maintaining vertical junction uniformity is the main challenge for fin-last. However, its impact on parasitic resistance and capacitances are small. Vertical junction non-uniformity is improved with source and drain recess and doping optimization.
UR - http://www.scopus.com/inward/record.url?scp=84891133837&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84891133837&partnerID=8YFLogxK
U2 - 10.1109/SISPAD.2013.6650596
DO - 10.1109/SISPAD.2013.6650596
M3 - Conference contribution
AN - SCOPUS:84891133837
SN - 9781467357364
T3 - International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
SP - 147
EP - 150
BT - 2013 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2013
T2 - 18th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2013
Y2 - 3 September 2013 through 5 September 2013
ER -