A complete logic BIST technology with no storage requirement

Wei Cheng Lien, Kuen-Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages of both pseudorandom and deterministic patterns. In order to apply the deterministic patterns, most traditional methods need to store some test data in external testers or on-chip memory. In this paper we present a novel mixed-mode BIST technique by which all deterministic patterns can be generated on chip in real time and thus requiring no storage device. By appropriately connecting some internal nets of the circuit under test to the inputs of the circuit, together with a set of pseudo-random patterns, this BIST scheme can reach full fault coverage in a very short time. Experimental results show that all irredundant stuck-at faults in each of the ISCAS85 benchmarks can be detected in less than 1000 test cycles with no storage space required.

Original languageEnglish
Title of host publicationProceedings - 2010 19th IEEE Asian Test Symposium, ATS 2010
Pages129-134
Number of pages6
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 19th IEEE Asian Test Symposium, ATS 2010 - Shanghai, China
Duration: 2010 Dec 12010 Dec 4

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other2010 19th IEEE Asian Test Symposium, ATS 2010
Country/TerritoryChina
CityShanghai
Period10-12-0110-12-04

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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