@inproceedings{4141a1d9e64c489ca44675a292caf00a,
title = "A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node",
abstract = "The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE∼2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.",
author = "Tang, {Y. T.} and Su, {C. J.} and Wang, {Y. S.} and Kao, {K. H.} and Wu, {T. L.} and Sung, {P. J.} and Hou, {F. J.} and Wang, {C. J.} and Yeh, {M. S.} and Lee, {Y. J.} and Wu, {W. F.} and Huang, {G. W.} and Shieh, {J. M.} and Yeh, {W. K.} and Wang, {Y. H.}",
note = "Funding Information: The authors would like to thank Prof. M. A. Alam, and Prof. C. Hu for the valuable comments. This work was support in part by the Ministry of Science and Technology, Taiwan (MOST-106-2633-E-009-001 and MOST 106-2221-E-492-034). Publisher Copyright: {\textcopyright} 2018 IEEE.; 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 ; Conference date: 18-06-2018 Through 22-06-2018",
year = "2018",
month = oct,
day = "25",
doi = "10.1109/VLSIT.2018.8510696",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "45--46",
booktitle = "2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018",
address = "United States",
}