A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node

Y. T. Tang, C. J. Su, Y. S. Wang, Kuo-Hsing Kao, T. L. Wu, P. J. Sung, F. J. Hou, C. J. Wang, M. S. Yeh, Y. J. Lee, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, Yeong-Her Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE∼2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.

Original languageEnglish
Title of host publication2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages45-46
Number of pages2
ISBN (Electronic)9781538642160
DOIs
Publication statusPublished - 2018 Oct 25
Event38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States
Duration: 2018 Jun 182018 Jun 22

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2018-June
ISSN (Print)0743-1562

Other

Other38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
CountryUnited States
CityHonolulu
Period18-06-1818-06-22

Fingerprint

Field effect transistors
Ferroelectric materials
Capacitance
Depolarization
Tensors
Phase transitions
Doping (additives)
Thermodynamics
Thin films
Oxides

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Tang, Y. T., Su, C. J., Wang, Y. S., Kao, K-H., Wu, T. L., Sung, P. J., ... Wang, Y-H. (2018). A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 45-46). [8510696] (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510696
Tang, Y. T. ; Su, C. J. ; Wang, Y. S. ; Kao, Kuo-Hsing ; Wu, T. L. ; Sung, P. J. ; Hou, F. J. ; Wang, C. J. ; Yeh, M. S. ; Lee, Y. J. ; Wu, W. F. ; Huang, G. W. ; Shieh, J. M. ; Yeh, W. K. ; Wang, Yeong-Her. / A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node. 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 45-46 (Digest of Technical Papers - Symposium on VLSI Technology).
@inproceedings{4141a1d9e64c489ca44675a292caf00a,
title = "A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node",
abstract = "The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE∼2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12{\%} Zr-doped HfO2.",
author = "Tang, {Y. T.} and Su, {C. J.} and Wang, {Y. S.} and Kuo-Hsing Kao and Wu, {T. L.} and Sung, {P. J.} and Hou, {F. J.} and Wang, {C. J.} and Yeh, {M. S.} and Lee, {Y. J.} and Wu, {W. F.} and Huang, {G. W.} and Shieh, {J. M.} and Yeh, {W. K.} and Yeong-Her Wang",
year = "2018",
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doi = "10.1109/VLSIT.2018.8510696",
language = "English",
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Tang, YT, Su, CJ, Wang, YS, Kao, K-H, Wu, TL, Sung, PJ, Hou, FJ, Wang, CJ, Yeh, MS, Lee, YJ, Wu, WF, Huang, GW, Shieh, JM, Yeh, WK & Wang, Y-H 2018, A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510696, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 45-46, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 18-06-18. https://doi.org/10.1109/VLSIT.2018.8510696

A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node. / Tang, Y. T.; Su, C. J.; Wang, Y. S.; Kao, Kuo-Hsing; Wu, T. L.; Sung, P. J.; Hou, F. J.; Wang, C. J.; Yeh, M. S.; Lee, Y. J.; Wu, W. F.; Huang, G. W.; Shieh, J. M.; Yeh, W. K.; Wang, Yeong-Her.

2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 45-46 8510696 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Tang, Y. T.

AU - Su, C. J.

AU - Wang, Y. S.

AU - Kao, Kuo-Hsing

AU - Wu, T. L.

AU - Sung, P. J.

AU - Hou, F. J.

AU - Wang, C. J.

AU - Yeh, M. S.

AU - Lee, Y. J.

AU - Wu, W. F.

AU - Huang, G. W.

AU - Shieh, J. M.

AU - Yeh, W. K.

AU - Wang, Yeong-Her

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N2 - The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE∼2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.

AB - The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE∼2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.

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M3 - Conference contribution

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T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 45

EP - 46

BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018

PB - Institute of Electrical and Electronics Engineers Inc.

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Tang YT, Su CJ, Wang YS, Kao K-H, Wu TL, Sung PJ et al. A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 45-46. 8510696. (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2018.8510696