A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs

Cheng-Wen Wu, P.-W. Luo, C.-K. Chen, Y.-H. Sung, W. Wu, H.-C. Shih, C.-H. Lee, K.-H. Lee, M.-W. Li, M.-C. Lung, C.-N. Lu, Y.-F. Chou, P.-L. Shih, C.-H. Ke, C. Shiah, P. Stolt, S. Tomishima, D.-M. Kwai, B.-D. Rong, N. LuS.-L. Lu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
Original languageEnglish
Title of host publicationIEEE Symp. VLSI Circuits (VLSI)
Publication statusPublished - 2015 Jun

Cite this

Wu, C-W., Luo, P-W., Chen, C-K., Sung, Y-H., Wu, W., Shih, H-C., ... Lu, S-L. (2015). A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs. In IEEE Symp. VLSI Circuits (VLSI)
Wu, Cheng-Wen ; Luo, P.-W. ; Chen, C.-K. ; Sung, Y.-H. ; Wu, W. ; Shih, H.-C. ; Lee, C.-H. ; Lee, K.-H. ; Li, M.-W. ; Lung, M.-C. ; Lu, C.-N. ; Chou, Y.-F. ; Shih, P.-L. ; Ke, C.-H. ; Shiah, C. ; Stolt, P. ; Tomishima, S. ; Kwai, D.-M. ; Rong, B.-D. ; Lu, N. ; Lu, S.-L. . / A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs. IEEE Symp. VLSI Circuits (VLSI). 2015.
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title = "A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs",
author = "Cheng-Wen Wu and P.-W. Luo and C.-K. Chen and Y.-H. Sung and W. Wu and H.-C. Shih and C.-H. Lee and K.-H. Lee and M.-W. Li and M.-C. Lung and C.-N. Lu and Y.-F. Chou and P.-L. Shih and C.-H. Ke and C. Shiah and P. Stolt and S. Tomishima and D.-M. Kwai and B.-D. Rong and N. Lu and S.-L. Lu",
year = "2015",
month = "6",
language = "English",
booktitle = "IEEE Symp. VLSI Circuits (VLSI)",

}

Wu, C-W, Luo, P-W, Chen, C-K, Sung, Y-H, Wu, W, Shih, H-C, Lee, C-H, Lee, K-H, Li, M-W, Lung, M-C, Lu, C-N, Chou, Y-F, Shih, P-L, Ke, C-H, Shiah, C, Stolt, P, Tomishima, S, Kwai, D-M, Rong, B-D, Lu, N & Lu, S-L 2015, A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs. in IEEE Symp. VLSI Circuits (VLSI).

A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs. / Wu, Cheng-Wen; Luo, P.-W. ; Chen, C.-K. ; Sung, Y.-H. ; Wu, W. ; Shih, H.-C. ; Lee, C.-H. ; Lee, K.-H. ; Li, M.-W. ; Lung, M.-C. ; Lu, C.-N. ; Chou, Y.-F. ; Shih, P.-L. ; Ke, C.-H. ; Shiah, C. ; Stolt, P. ; Tomishima, S. ; Kwai, D.-M. ; Rong, B.-D. ; Lu, N. ; Lu, S.-L. .

IEEE Symp. VLSI Circuits (VLSI). 2015.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs

AU - Wu, Cheng-Wen

AU - Luo, P.-W.

AU - Chen, C.-K.

AU - Sung, Y.-H.

AU - Wu, W.

AU - Shih, H.-C.

AU - Lee, C.-H.

AU - Lee, K.-H.

AU - Li, M.-W.

AU - Lung, M.-C.

AU - Lu, C.-N.

AU - Chou, Y.-F.

AU - Shih, P.-L.

AU - Ke, C.-H.

AU - Shiah, C.

AU - Stolt, P.

AU - Tomishima, S.

AU - Kwai, D.-M.

AU - Rong, B.-D.

AU - Lu, N.

AU - Lu, S.-L.

PY - 2015/6

Y1 - 2015/6

M3 - Conference contribution

BT - IEEE Symp. VLSI Circuits (VLSI)

ER -

Wu C-W, Luo P-W, Chen C-K, Sung Y-H, Wu W, Shih H-C et al. A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs. In IEEE Symp. VLSI Circuits (VLSI). 2015