Abstract
Large input voltage range and wide output current range are usually needed for dc-dc converters. For these input and output conditions, the converter's efficiency can be maximized by a proposed method, efficiency-optimized switching-frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by the low-complexity and low-power EOF generator. A reconfigurable compensator is developed for improving the load regulation and the transient response. A piecewise-linear current sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the aforementioned three proposed methods, a monolithic current-mode dc-dc buck converter is implemented in a 0.35-μm 3.3-V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16 and 15mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40 mV and 12 μs, respectively, while the PLCS can reduce 3mW of power loss. Compared with other published converters in 0.35-μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97mm 2.
| Original language | English |
|---|---|
| Article number | 5954187 |
| Pages (from-to) | 869-880 |
| Number of pages | 12 |
| Journal | IEEE Transactions on Power Electronics |
| Volume | 27 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2012 Jan 16 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
}
A current-mode DC-DC buck converter with efficiency-optimized frequency control and reconfigurable compensation. / Liu, Jia Ming; Wang, Pai Yi; Kuo, Tai-Haur.
In: IEEE Transactions on Power Electronics, Vol. 27, No. 2, 5954187, 16.01.2012, p. 869-880.Research output: Contribution to journal › Article
TY - JOUR
T1 - A current-mode DC-DC buck converter with efficiency-optimized frequency control and reconfigurable compensation
AU - Liu, Jia Ming
AU - Wang, Pai Yi
AU - Kuo, Tai-Haur
PY - 2012/1/16
Y1 - 2012/1/16
N2 - Large input voltage range and wide output current range are usually needed for dc-dc converters. For these input and output conditions, the converter's efficiency can be maximized by a proposed method, efficiency-optimized switching-frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by the low-complexity and low-power EOF generator. A reconfigurable compensator is developed for improving the load regulation and the transient response. A piecewise-linear current sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the aforementioned three proposed methods, a monolithic current-mode dc-dc buck converter is implemented in a 0.35-μm 3.3-V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16 and 15mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40 mV and 12 μs, respectively, while the PLCS can reduce 3mW of power loss. Compared with other published converters in 0.35-μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97mm 2.
AB - Large input voltage range and wide output current range are usually needed for dc-dc converters. For these input and output conditions, the converter's efficiency can be maximized by a proposed method, efficiency-optimized switching-frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by the low-complexity and low-power EOF generator. A reconfigurable compensator is developed for improving the load regulation and the transient response. A piecewise-linear current sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the aforementioned three proposed methods, a monolithic current-mode dc-dc buck converter is implemented in a 0.35-μm 3.3-V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16 and 15mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40 mV and 12 μs, respectively, while the PLCS can reduce 3mW of power loss. Compared with other published converters in 0.35-μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97mm 2.
UR - http://www.scopus.com/inward/record.url?scp=84862950768&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84862950768&partnerID=8YFLogxK
U2 - 10.1109/TPEL.2011.2162079
DO - 10.1109/TPEL.2011.2162079
M3 - Article
AN - SCOPUS:84862950768
VL - 27
SP - 869
EP - 880
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
SN - 0885-8993
IS - 2
M1 - 5954187
ER -