TY - JOUR
T1 - A current-mode DC-DC buck converter with efficiency-optimized frequency control and reconfigurable compensation
AU - Liu, Jia Ming
AU - Wang, Pai Yi
AU - Kuo, Tai Haur
N1 - Funding Information:
Manuscript received July 30, 2010; revised October 9, 2010 and May 19, 2011; accepted July 2, 2011. Date of current version January 9, 2012. This work was supported by the National Science Council of Taiwan under Grant NSC 98-2218-E-006-242 and Grant NSC 99-3113-P-006-004. Recommended for publication by Associate Editor S. Y. (Ron) Hui.
PY - 2012
Y1 - 2012
N2 - Large input voltage range and wide output current range are usually needed for dc-dc converters. For these input and output conditions, the converter's efficiency can be maximized by a proposed method, efficiency-optimized switching-frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by the low-complexity and low-power EOF generator. A reconfigurable compensator is developed for improving the load regulation and the transient response. A piecewise-linear current sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the aforementioned three proposed methods, a monolithic current-mode dc-dc buck converter is implemented in a 0.35-μm 3.3-V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16 and 15mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40 mV and 12 μs, respectively, while the PLCS can reduce 3mW of power loss. Compared with other published converters in 0.35-μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97mm 2.
AB - Large input voltage range and wide output current range are usually needed for dc-dc converters. For these input and output conditions, the converter's efficiency can be maximized by a proposed method, efficiency-optimized switching-frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by the low-complexity and low-power EOF generator. A reconfigurable compensator is developed for improving the load regulation and the transient response. A piecewise-linear current sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the aforementioned three proposed methods, a monolithic current-mode dc-dc buck converter is implemented in a 0.35-μm 3.3-V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16 and 15mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40 mV and 12 μs, respectively, while the PLCS can reduce 3mW of power loss. Compared with other published converters in 0.35-μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97mm 2.
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U2 - 10.1109/TPEL.2011.2162079
DO - 10.1109/TPEL.2011.2162079
M3 - Article
AN - SCOPUS:84862950768
SN - 0885-8993
VL - 27
SP - 869
EP - 880
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 2
M1 - 5954187
ER -