A current-recycling technique for shadow-match-line sensing in content-addressable memories

Jian Wei Zhang, Yi Zheng Ye, Bin-Da Liu

Research output: Contribution to journalArticle

19 Citations (Scopus)

Abstract

A current-recycling technique for shadow-match-line (SML) sensing in content-addressable memories (CAMs) is presented. In order to minimize energy-overhead, a novel current-recycling voltage detector (CRVD) is devised, whose working current is reused to charge up the match-line (ML) to determine matches or mismatches. Furthermore, with this CRVD, the word circuits realize fast-disable of the charging paths in case of mismatches. Since the majority of CAM words are mismatched, a significant power is reduced with a high search speed. Pre-layout simulation results show the proposed 256-word X 144-bit ternary CAM, based on a 0.13-μm 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900-ps search time. The achievement illustrates a 74.2% energy-delay-product (EDP) reduction as compared with the speed-optimized current-saving scheme. Post-layout simulation results of the word circuits show 0.65 fJ/bit/search energy per search with 1.2-ns search time.

Original languageEnglish
Article number4526715
Pages (from-to)677-682
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume16
Issue number6
DOIs
Publication statusPublished - 2008 Jun 1

Fingerprint

Associative storage
Recycling
Networks (circuits)
Detectors
Electric potential

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

@article{085610ab88654ff48d10893a826fe50d,
title = "A current-recycling technique for shadow-match-line sensing in content-addressable memories",
abstract = "A current-recycling technique for shadow-match-line (SML) sensing in content-addressable memories (CAMs) is presented. In order to minimize energy-overhead, a novel current-recycling voltage detector (CRVD) is devised, whose working current is reused to charge up the match-line (ML) to determine matches or mismatches. Furthermore, with this CRVD, the word circuits realize fast-disable of the charging paths in case of mismatches. Since the majority of CAM words are mismatched, a significant power is reduced with a high search speed. Pre-layout simulation results show the proposed 256-word X 144-bit ternary CAM, based on a 0.13-μm 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900-ps search time. The achievement illustrates a 74.2{\%} energy-delay-product (EDP) reduction as compared with the speed-optimized current-saving scheme. Post-layout simulation results of the word circuits show 0.65 fJ/bit/search energy per search with 1.2-ns search time.",
author = "Zhang, {Jian Wei} and Ye, {Yi Zheng} and Bin-Da Liu",
year = "2008",
month = "6",
day = "1",
doi = "10.1109/TVLSI.2008.2000247",
language = "English",
volume = "16",
pages = "677--682",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",

}

A current-recycling technique for shadow-match-line sensing in content-addressable memories. / Zhang, Jian Wei; Ye, Yi Zheng; Liu, Bin-Da.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 6, 4526715, 01.06.2008, p. 677-682.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A current-recycling technique for shadow-match-line sensing in content-addressable memories

AU - Zhang, Jian Wei

AU - Ye, Yi Zheng

AU - Liu, Bin-Da

PY - 2008/6/1

Y1 - 2008/6/1

N2 - A current-recycling technique for shadow-match-line (SML) sensing in content-addressable memories (CAMs) is presented. In order to minimize energy-overhead, a novel current-recycling voltage detector (CRVD) is devised, whose working current is reused to charge up the match-line (ML) to determine matches or mismatches. Furthermore, with this CRVD, the word circuits realize fast-disable of the charging paths in case of mismatches. Since the majority of CAM words are mismatched, a significant power is reduced with a high search speed. Pre-layout simulation results show the proposed 256-word X 144-bit ternary CAM, based on a 0.13-μm 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900-ps search time. The achievement illustrates a 74.2% energy-delay-product (EDP) reduction as compared with the speed-optimized current-saving scheme. Post-layout simulation results of the word circuits show 0.65 fJ/bit/search energy per search with 1.2-ns search time.

AB - A current-recycling technique for shadow-match-line (SML) sensing in content-addressable memories (CAMs) is presented. In order to minimize energy-overhead, a novel current-recycling voltage detector (CRVD) is devised, whose working current is reused to charge up the match-line (ML) to determine matches or mismatches. Furthermore, with this CRVD, the word circuits realize fast-disable of the charging paths in case of mismatches. Since the majority of CAM words are mismatched, a significant power is reduced with a high search speed. Pre-layout simulation results show the proposed 256-word X 144-bit ternary CAM, based on a 0.13-μm 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900-ps search time. The achievement illustrates a 74.2% energy-delay-product (EDP) reduction as compared with the speed-optimized current-saving scheme. Post-layout simulation results of the word circuits show 0.65 fJ/bit/search energy per search with 1.2-ns search time.

UR - http://www.scopus.com/inward/record.url?scp=44249098522&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=44249098522&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2008.2000247

DO - 10.1109/TVLSI.2008.2000247

M3 - Article

AN - SCOPUS:44249098522

VL - 16

SP - 677

EP - 682

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 6

M1 - 4526715

ER -