A current reuse quadrature GPS receiver in 0.13 μm CMOS

Kuang-Wei Cheng, Karthik Natarajan, David J. Allstot

Research output: Contribution to journalArticle

39 Citations (Scopus)

Abstract

A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT Σ Δ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ MHz frequency offset with quadrature error less than 1°.

Original languageEnglish
Article number5419194
Pages (from-to)510-523
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number3
DOIs
Publication statusPublished - 2010 Mar 1

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Variable frequency oscillators
Digital to analog conversion
Phase noise
Global positioning system
Mixer circuits
Phase locked loops
Resistors
Electric power utilization
Topology
Feedback

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Cheng, Kuang-Wei ; Natarajan, Karthik ; Allstot, David J. / A current reuse quadrature GPS receiver in 0.13 μm CMOS. In: IEEE Journal of Solid-State Circuits. 2010 ; Vol. 45, No. 3. pp. 510-523.
@article{3527d632a1dd43a98d028d28842f5c11,
title = "A current reuse quadrature GPS receiver in 0.13 μm CMOS",
abstract = "A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT Σ Δ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ MHz frequency offset with quadrature error less than 1°.",
author = "Kuang-Wei Cheng and Karthik Natarajan and Allstot, {David J.}",
year = "2010",
month = "3",
day = "1",
doi = "10.1109/JSSC.2009.2039272",
language = "English",
volume = "45",
pages = "510--523",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

A current reuse quadrature GPS receiver in 0.13 μm CMOS. / Cheng, Kuang-Wei; Natarajan, Karthik; Allstot, David J.

In: IEEE Journal of Solid-State Circuits, Vol. 45, No. 3, 5419194, 01.03.2010, p. 510-523.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A current reuse quadrature GPS receiver in 0.13 μm CMOS

AU - Cheng, Kuang-Wei

AU - Natarajan, Karthik

AU - Allstot, David J.

PY - 2010/3/1

Y1 - 2010/3/1

N2 - A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT Σ Δ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ MHz frequency offset with quadrature error less than 1°.

AB - A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT Σ Δ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ MHz frequency offset with quadrature error less than 1°.

UR - http://www.scopus.com/inward/record.url?scp=77649127080&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77649127080&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2009.2039272

DO - 10.1109/JSSC.2009.2039272

M3 - Article

AN - SCOPUS:77649127080

VL - 45

SP - 510

EP - 523

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 3

M1 - 5419194

ER -