A design of linearity built-in self-test for current-steering DAC

Hsin Wen Ting; Soon Jyh Chang; Su Ling Huang

doi:10.1007/s10836-010-5187-2

A design of linearity built-in self-test for current-steering DAC

Hsin Wen Ting, Soon Jyh Chang, Su Ling Huang

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.

Original language	English
Pages (from-to)	85-94
Number of pages	10
Journal	Journal of Electronic Testing: Theory and Applications (JETTA)
Volume	27
Issue number	1
DOIs	https://doi.org/10.1007/s10836-010-5187-2
Publication status	Published - 2011 Feb 1

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1007/s10836-010-5187-2

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abstract = "In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.",

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