TY - GEN
T1 - A Digital Multiphase Converter with Sensor-less Current and Thermal Balance Mechanism
AU - Hu, Kai Yu
AU - Chen, Yu Sin
AU - Tsai, Chien Hung
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/12/14
Y1 - 2018/12/14
N2 - This paper presents a sensor-less approach to achieve current balance and thermal balance in a digital voltage mode controlled four-phase buck converter. Rather than utilize current and temperature sensors to gather the current and thermal information as most of previous researches, the sensor-less equivalent resistance (R eq ) ratio estimation is used in this work to obtain the current and thermal information implicitly. Based on the estimative results, the duty offset is further calculated and compensated for each phase to carry out either equal current sharing or uniform thermal distribution. The digital controller was manufactured by TSMC 0.18-μm 1P6M standard CMOS process. The experimental results are proved the practicability of the proposed balancing mechanism. The current balance scheme improves the current sharing error from 35% to 6.3%, while the thermal balance technique narrows down the peak temperature difference from 6.6°C to 1.8°C.
AB - This paper presents a sensor-less approach to achieve current balance and thermal balance in a digital voltage mode controlled four-phase buck converter. Rather than utilize current and temperature sensors to gather the current and thermal information as most of previous researches, the sensor-less equivalent resistance (R eq ) ratio estimation is used in this work to obtain the current and thermal information implicitly. Based on the estimative results, the duty offset is further calculated and compensated for each phase to carry out either equal current sharing or uniform thermal distribution. The digital controller was manufactured by TSMC 0.18-μm 1P6M standard CMOS process. The experimental results are proved the practicability of the proposed balancing mechanism. The current balance scheme improves the current sharing error from 35% to 6.3%, while the thermal balance technique narrows down the peak temperature difference from 6.6°C to 1.8°C.
UR - http://www.scopus.com/inward/record.url?scp=85060478517&partnerID=8YFLogxK
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U2 - 10.1109/ASSCC.2018.8579301
DO - 10.1109/ASSCC.2018.8579301
M3 - Conference contribution
AN - SCOPUS:85060478517
T3 - 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
SP - 175
EP - 178
BT - 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
Y2 - 5 November 2018 through 7 November 2018
ER -