A digitally calibrated CMOS transconductor with a 100-MHz bandwidth and 75-dB SFDR

Soon Jyh Chang; Ying Zu Lin; Yen Ting Liu

doi:10.1109/TCSII.2008.2001987

A digitally calibrated CMOS transconductor with a 100-MHz bandwidth and 75-dB SFDR

Soon Jyh Chang, Ying Zu Lin, Yen Ting Liu

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current-voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-μ CMOS process, the transconductor occupies 220×160 μ² active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption.

Original language	English
Pages (from-to)	1089-1093
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	55
Issue number	11
DOIs	https://doi.org/10.1109/TCSII.2008.2001987
Publication status	Published - 2008

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2008.2001987

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title = "A digitally calibrated CMOS transconductor with a 100-MHz bandwidth and 75-dB SFDR",

abstract = "This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current-voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-μ CMOS process, the transconductor occupies 220×160 μ2 active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption.",

author = "Chang, {Soon Jyh} and Lin, {Ying Zu} and Liu, {Yen Ting}",

note = "Funding Information: Manuscript received January 25, 2008; revised April 24, 2008. Current version published December 10, 2008. This work was supported by the National Science Council of Taiwan under Grant NSC-96–2221-E-006–294-MY2. This paper was recommended by Associate Editor G. A. Rincon-Mora.",

year = "2008",

doi = "10.1109/TCSII.2008.2001987",

language = "English",

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pages = "1089--1093",

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AU - Chang, Soon Jyh

AU - Lin, Ying Zu

AU - Liu, Yen Ting

N1 - Funding Information: Manuscript received January 25, 2008; revised April 24, 2008. Current version published December 10, 2008. This work was supported by the National Science Council of Taiwan under Grant NSC-96–2221-E-006–294-MY2. This paper was recommended by Associate Editor G. A. Rincon-Mora.

PY - 2008

Y1 - 2008

N2 - This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current-voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-μ CMOS process, the transconductor occupies 220×160 μ2 active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption.

AB - This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current-voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-μ CMOS process, the transconductor occupies 220×160 μ2 active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption.

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ER -

A digitally calibrated CMOS transconductor with a 100-MHz bandwidth and 75-dB SFDR

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