A digitally calibrated CMOS transconductor with a 100-MHz bandwidth and 75-dB SFDR

Soon Jyh Chang, Ying Zu Lin, Yen Ting Liu

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current-voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-μ CMOS process, the transconductor occupies 220×160 μ2 active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption.

Original languageEnglish
Pages (from-to)1089-1093
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume55
Issue number11
DOIs
Publication statusPublished - 2008 Dec 30

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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