TY - GEN
T1 - A digitally controlled buck converter with current sensor-less adaptive voltage positioning (AVP) mechanism
AU - Hu, Kai Yu
AU - Chen, Bo Ming
AU - Tsai, Chien Hung
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/6/5
Y1 - 2017/6/5
N2 - Adaptive voltage positioning (AVP) technique has been widely used in voltage regulator (VR) applications. In this paper, a digitally controlled buck converter with the proposed current sensor-less AVP technique is presented. Without the need for sensing or sampling the loading condition, the proposed control architecture utilizes the error signal of the digitalized controller to obtain the current information. The elimination of a current analog-to-digital converter (ADC) or any current sensing circuits significantly reduced the size and cost of the digital controller. A 781.25-kHz, single-phase synchronous buck converter which the input voltage is ranging from 2.7 to 4.2 V and an optional output between 0.9 to 1.2 V was implemented using the field-programmable gate array (FPGA). Experimental results show that an optimal AVP function was achieved in transient response to a 200-650 mA step load change within 30 μs.
AB - Adaptive voltage positioning (AVP) technique has been widely used in voltage regulator (VR) applications. In this paper, a digitally controlled buck converter with the proposed current sensor-less AVP technique is presented. Without the need for sensing or sampling the loading condition, the proposed control architecture utilizes the error signal of the digitalized controller to obtain the current information. The elimination of a current analog-to-digital converter (ADC) or any current sensing circuits significantly reduced the size and cost of the digital controller. A 781.25-kHz, single-phase synchronous buck converter which the input voltage is ranging from 2.7 to 4.2 V and an optional output between 0.9 to 1.2 V was implemented using the field-programmable gate array (FPGA). Experimental results show that an optimal AVP function was achieved in transient response to a 200-650 mA step load change within 30 μs.
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U2 - 10.1109/VLSI-DAT.2017.7939664
DO - 10.1109/VLSI-DAT.2017.7939664
M3 - Conference contribution
AN - SCOPUS:85021393962
T3 - 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
BT - 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
Y2 - 24 April 2017 through 27 April 2017
ER -