Resistance-based memory devices are considered as a strong candidate for next-generation nonvolatile memories as well as potential application in high density embedded cache. These devices can be programmed to different resistance states by applying electrical bias. Read operation then senses the programmed state by discharging a shared data line through the memory cell. However, as the dimensions of the device scale down, its resistance increases and the distribution widens, which leads to reduced sensing margins and degradation in read performance. In the proposed dual-data line (DDL) read scheme, we recycle current flowing through the memory cell during the read operation to create an additional voltage swing on a secondary data line, and combine it with the signal on the original data line to reduce sensing time and energy. Performance comparison with the conventional read scheme is derived theoretically by using circuit analysis and verified through simulation on an array critical path constructed in 65-nm technology. Results show that the DDL scheme can improve sensing margins by an average of 86%, which translates to a sensing time reduction of 47%, across various device conditions. For the same read performance, the sensing energy is decreased by 48%.
|Number of pages||8|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2018 Feb|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering