A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

Jih Ren Goh, Yen Long Lee, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519∗0.137 mm2 and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.

Original languageEnglish
Title of host publication2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479962754
DOIs
Publication statusPublished - 2015 May 28
Event2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan
Duration: 2015 Apr 272015 Apr 29

Publication series

Name2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Other

Other2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
CountryTaiwan
CityHsinchu
Period15-04-2715-04-29

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Goh, J. R., Lee, Y. L., & Chang, S-J. (2015). A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 [7114500] (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2015.7114500