A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

Jih Ren Goh; Yen Long Lee; Soon Jyh Chang

doi:10.1109/VLSI-DAT.2015.7114500

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

Jih Ren Goh
, Yen Long Lee
, Soon Jyh Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519∗0.137 mm² and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.

Original language	English
Title of host publication	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479962754
DOIs	https://doi.org/10.1109/VLSI-DAT.2015.7114500
Publication status	Published - 2015 May 28
Event	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan Duration: 2015 Apr 27 → 2015 Apr 29

Publication series

Name	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Other

Other	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Country/Territory	Taiwan
City	Hsinchu
Period	15-04-27 → 15-04-29

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-DAT.2015.7114500

Cite this

Goh, J. R., Lee, Y. L., & Chang, S. J. (2015). A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 Article 7114500 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2015.7114500

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title = "A dual-edge sampling CES delay-locked loop based clock and data recovery circuits",

abstract = "This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519∗0.137 mm2 and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.",

author = "Goh, \{Jih Ren\} and Lee, \{Yen Long\} and Chang, \{Soon Jyh\}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 ; Conference date: 27-04-2015 Through 29-04-2015",

year = "2015",

month = may,

day = "28",

doi = "10.1109/VLSI-DAT.2015.7114500",

language = "English",

series = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",

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address = "United States",

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Goh, JR, Lee, YL & Chang, SJ 2015, A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. in 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015., 7114500, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, 15-04-27. https://doi.org/10.1109/VLSI-DAT.2015.7114500

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. / Goh, Jih Ren; Lee, Yen Long; Chang, Soon Jyh.
2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7114500 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Goh, Jih Ren

AU - Lee, Yen Long

AU - Chang, Soon Jyh

PY - 2015/5/28

Y1 - 2015/5/28

N2 - This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519∗0.137 mm2 and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.

AB - This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519∗0.137 mm2 and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.

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M3 - Conference contribution

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T3 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

BT - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Y2 - 27 April 2015 through 29 April 2015

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Goh JR, Lee YL, Chang SJ. A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7114500. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). doi: 10.1109/VLSI-DAT.2015.7114500

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

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