A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs

Yen Long Lee; Yu Po Cheng; Soon Jyh Chang; Hsin Wen Ting

doi:10.1109/MDAT.2017.2753700

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs

Yen Long Lee, Yu Po Cheng, Soon Jyh Chang, Hsin Wen Ting

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

Editor's note: Analysis of jitter tolerance of CDR circuit is important for high-speed serial link design. This article presents a simple yet effective method for evaluating the tracking capability of CDR, which is applied to the analysis.-Youngsoo Shin, KAIST.

Original language	English
Article number	8039277
Pages (from-to)	63-73
Number of pages	11
Journal	IEEE Design and Test
Volume	35
Issue number	1
DOIs	https://doi.org/10.1109/MDAT.2017.2753700
Publication status	Published - 2018 Feb

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MDAT.2017.2753700

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title = "A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs",

abstract = "Editor's note: Analysis of jitter tolerance of CDR circuit is important for high-speed serial link design. This article presents a simple yet effective method for evaluating the tracking capability of CDR, which is applied to the analysis.-Youngsoo Shin, KAIST.",

author = "Lee, {Yen Long} and Cheng, {Yu Po} and Chang, {Soon Jyh} and Ting, {Hsin Wen}",

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year = "2018",

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A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs

Abstract

All Science Journal Classification (ASJC) codes

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