A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs

Yen Long Lee; Yu Po Cheng; Soon Jyh Chang; Hsin Wen Ting

doi:10.1109/MDAT.2017.2753700

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs

Yen Long Lee, Yu Po Cheng, Soon Jyh Chang, Hsin Wen Ting

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

Editor's note: Analysis of jitter tolerance of CDR circuit is important for high-speed serial link design. This article presents a simple yet effective method for evaluating the tracking capability of CDR, which is applied to the analysis.-Youngsoo Shin, KAIST.

Original language	English
Article number	8039277
Pages (from-to)	63-73
Number of pages	11
Journal	IEEE Design and Test
Volume	35
Issue number	1
DOIs	https://doi.org/10.1109/MDAT.2017.2753700
Publication status	Published - 2018 Feb

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MDAT.2017.2753700

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@article{8174800cd57b401182cc1c953d6497d9,

title = "A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs",

abstract = "Editor's note: Analysis of jitter tolerance of CDR circuit is important for high-speed serial link design. This article presents a simple yet effective method for evaluating the tracking capability of CDR, which is applied to the analysis.-Youngsoo Shin, KAIST.",

author = "Lee, {Yen Long} and Cheng, {Yu Po} and Chang, {Soon Jyh} and Ting, {Hsin Wen}",

note = "Funding Information: We would like to thank Himax Technologies Inc., Taiwan. This work was supported in part by the Ministry of Science and Technology of Taiwan under Grant Numbers MOST 105-2221-E-006-240-MY3 and MOST 106-2221-E-151-050-MY2. Publisher Copyright: {\textcopyright} 2013 IEEE.",

year = "2018",

month = feb,

doi = "10.1109/MDAT.2017.2753700",

language = "English",

volume = "35",

pages = "63--73",

journal = "IEEE Design and Test",

issn = "2168-2356",

publisher = "IEEE Computer Society",

number = "1",

}

TY - JOUR

T1 - A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs

AU - Lee, Yen Long

AU - Cheng, Yu Po

AU - Chang, Soon Jyh

AU - Ting, Hsin Wen

N1 - Funding Information: We would like to thank Himax Technologies Inc., Taiwan. This work was supported in part by the Ministry of Science and Technology of Taiwan under Grant Numbers MOST 105-2221-E-006-240-MY3 and MOST 106-2221-E-151-050-MY2. Publisher Copyright: © 2013 IEEE.

PY - 2018/2

Y1 - 2018/2

N2 - Editor's note: Analysis of jitter tolerance of CDR circuit is important for high-speed serial link design. This article presents a simple yet effective method for evaluating the tracking capability of CDR, which is applied to the analysis.-Youngsoo Shin, KAIST.

AB - Editor's note: Analysis of jitter tolerance of CDR circuit is important for high-speed serial link design. This article presents a simple yet effective method for evaluating the tracking capability of CDR, which is applied to the analysis.-Youngsoo Shin, KAIST.

UR - http://www.scopus.com/inward/record.url?scp=85030647545&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85030647545&partnerID=8YFLogxK

U2 - 10.1109/MDAT.2017.2753700

DO - 10.1109/MDAT.2017.2753700

M3 - Article

AN - SCOPUS:85030647545

VL - 35

SP - 63

EP - 73

JO - IEEE Design and Test

JF - IEEE Design and Test

SN - 2168-2356

IS - 1

M1 - 8039277

ER -

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs

Abstract

All Science Journal Classification (ASJC) codes

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