A fast testing method for sequential circuits at the state transition level

Wei Lun Wang, Jhing Fa Wang, Kuen-Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper an efficient method called the fast augmented state transition (FAST) test method is proposed to alleviate the testing problem of sequential circuits at the state transition level. By adding some extra logic gates to a sequential circuit under test the FAST method guarantees that each state of the augmented circuit has both the shortest distinguishing and synchronizing sequences, hence the testing complexity can be greatly reduced. The test length of the FAST method is shorter than any other exhaustive testing approaches based on the state transition level. Furthermore the test set for the augmented circuit can be easily identified.

Original languageEnglish
Title of host publicationProceedings International Test Conference, ITC 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages514-519
Number of pages6
ISBN (Electronic)9780780307605
DOIs
Publication statusPublished - 1992 Jan 1
EventInternational Test Conference, ITC 1992 - Baltimore, United States
Duration: 1992 Sep 201992 Sep 24

Publication series

NameProceedings - International Test Conference
Volume1992-January
ISSN (Print)1089-3539

Other

OtherInternational Test Conference, ITC 1992
CountryUnited States
CityBaltimore
Period92-09-2092-09-24

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Wang, W. L., Wang, J. F., & Lee, K-J. (1992). A fast testing method for sequential circuits at the state transition level. In Proceedings International Test Conference, ITC 1992 (pp. 514-519). [527863] (Proceedings - International Test Conference; Vol. 1992-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEST.1992.527863