A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer

Tien Feng Hsu; Chun Po Huang; I. Jen Chao; Soon Jyh Chang

doi:10.1109/VLSI-DAT.2015.7114518

A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer

Tien Feng Hsu, Chun Po Huang, I. Jen Chao, Soon Jyh Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a comparator-based OTA first-order discrete-time low-distortion sigma-delta modulator. A split data weighted averaging (DWA) algorithm logic is proposed to release the heavy burden of digital circuit while a 6 bit DAC is implemented in this work. In addition, a comparator-based OTA is used to reduce the power consumption. On the top of that, to achieve lower power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. The modulator core occupies an active area of 0.0275 mm² in TSMC 90-nm 1P9M CMOS process. Experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.

Original language	English
Title of host publication	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479962754
DOIs	https://doi.org/10.1109/VLSI-DAT.2015.7114518
Publication status	Published - 2015 May 28
Event	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan Duration: 2015 Apr 27 → 2015 Apr 29

Publication series

Name	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Other

Other	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Country/Territory	Taiwan
City	Hsinchu
Period	15-04-27 → 15-04-29

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-DAT.2015.7114518

Cite this

Hsu, T. F., Huang, C. P., Chao, I. J., & Chang, S. J. (2015). A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 Article 7114518 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2015.7114518

Hsu, Tien Feng ; Huang, Chun Po ; Chao, I. Jen et al. / A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer. 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

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title = "A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer",

abstract = "This paper presents a comparator-based OTA first-order discrete-time low-distortion sigma-delta modulator. A split data weighted averaging (DWA) algorithm logic is proposed to release the heavy burden of digital circuit while a 6 bit DAC is implemented in this work. In addition, a comparator-based OTA is used to reduce the power consumption. On the top of that, to achieve lower power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. The modulator core occupies an active area of 0.0275 mm2 in TSMC 90-nm 1P9M CMOS process. Experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.",

author = "Hsu, {Tien Feng} and Huang, {Chun Po} and Chao, {I. Jen} and Chang, {Soon Jyh}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 ; Conference date: 27-04-2015 Through 29-04-2015",

year = "2015",

month = may,

day = "28",

doi = "10.1109/VLSI-DAT.2015.7114518",

language = "English",

series = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",

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Hsu, TF, Huang, CP, Chao, IJ & Chang, SJ 2015, A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer. in 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015., 7114518, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, 15-04-27. https://doi.org/10.1109/VLSI-DAT.2015.7114518

A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer. / Hsu, Tien Feng; Huang, Chun Po; Chao, I. Jen et al.
2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7114518 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer

AU - Hsu, Tien Feng

AU - Huang, Chun Po

AU - Chao, I. Jen

AU - Chang, Soon Jyh

PY - 2015/5/28

Y1 - 2015/5/28

N2 - This paper presents a comparator-based OTA first-order discrete-time low-distortion sigma-delta modulator. A split data weighted averaging (DWA) algorithm logic is proposed to release the heavy burden of digital circuit while a 6 bit DAC is implemented in this work. In addition, a comparator-based OTA is used to reduce the power consumption. On the top of that, to achieve lower power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. The modulator core occupies an active area of 0.0275 mm2 in TSMC 90-nm 1P9M CMOS process. Experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.

AB - This paper presents a comparator-based OTA first-order discrete-time low-distortion sigma-delta modulator. A split data weighted averaging (DWA) algorithm logic is proposed to release the heavy burden of digital circuit while a 6 bit DAC is implemented in this work. In addition, a comparator-based OTA is used to reduce the power consumption. On the top of that, to achieve lower power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. The modulator core occupies an active area of 0.0275 mm2 in TSMC 90-nm 1P9M CMOS process. Experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.

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Hsu TF, Huang CP, Chao IJ, Chang SJ. A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7114518. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). doi: 10.1109/VLSI-DAT.2015.7114518

A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer

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