A fuzzy neural network chip based on systolic array architecture

Jiahn Jung Chen; Yau Hwang Kuo; Cheng I. Kao

doi:10.1109/ASIC.1992.270195

A fuzzy neural network chip based on systolic array architecture

Jiahn Jung Chen, Yau Hwang Kuo, Cheng I. Kao

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A neural network model using a fuzzy classification concept, called FNN, is proposed. The design of an ASIC that implements that FNN model is presented. The chip architecture is based on a one-dimensional systolic array architecture, which provides a low-cost and high-performance parallel inference scheme. The high-level synthesis technique is adopted to design the ASIC, and VHSIC hardware description language (VHDL) is used to model it at the behavior domain.

Original language	English
Title of host publication	Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
Publisher	IEEE Computer Society
Pages	577-580
Number of pages	4
ISBN (Electronic)	0780307682
DOIs	https://doi.org/10.1109/ASIC.1992.270195
Publication status	Published - 1992
Event	5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 - Rochester, United States Duration: 1992 Sept 21 → 1992 Sept 25

Publication series

Name	Proceedings of International Conference on ASIC
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Conference

Conference	5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
Country/Territory	United States
City	Rochester
Period	92-09-21 → 92-09-25

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASIC.1992.270195

Cite this

@inproceedings{e3f5a72dd7d34ed8b3a73f00e5f09f7d,

title = "A fuzzy neural network chip based on systolic array architecture",

abstract = "A neural network model using a fuzzy classification concept, called FNN, is proposed. The design of an ASIC that implements that FNN model is presented. The chip architecture is based on a one-dimensional systolic array architecture, which provides a low-cost and high-performance parallel inference scheme. The high-level synthesis technique is adopted to design the ASIC, and VHSIC hardware description language (VHDL) is used to model it at the behavior domain.",

author = "Chen, {Jiahn Jung} and Kuo, {Yau Hwang} and Kao, {Cheng I.}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 ; Conference date: 21-09-1992 Through 25-09-1992",

year = "1992",

doi = "10.1109/ASIC.1992.270195",

language = "English",

series = "Proceedings of International Conference on ASIC",

publisher = "IEEE Computer Society",

pages = "577--580",

booktitle = "Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992",

address = "United States",

}

Chen, JJ, Kuo, YH & Kao, CI 1992, A fuzzy neural network chip based on systolic array architecture. in Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992., 270195, Proceedings of International Conference on ASIC, IEEE Computer Society, pp. 577-580, 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992, Rochester, United States, 92-09-21. https://doi.org/10.1109/ASIC.1992.270195

A fuzzy neural network chip based on systolic array architecture. / Chen, Jiahn Jung; Kuo, Yau Hwang; Kao, Cheng I.

Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992. IEEE Computer Society, 1992. p. 577-580 270195 (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A fuzzy neural network chip based on systolic array architecture

AU - Chen, Jiahn Jung

AU - Kuo, Yau Hwang

AU - Kao, Cheng I.

PY - 1992

Y1 - 1992

N2 - A neural network model using a fuzzy classification concept, called FNN, is proposed. The design of an ASIC that implements that FNN model is presented. The chip architecture is based on a one-dimensional systolic array architecture, which provides a low-cost and high-performance parallel inference scheme. The high-level synthesis technique is adopted to design the ASIC, and VHSIC hardware description language (VHDL) is used to model it at the behavior domain.

AB - A neural network model using a fuzzy classification concept, called FNN, is proposed. The design of an ASIC that implements that FNN model is presented. The chip architecture is based on a one-dimensional systolic array architecture, which provides a low-cost and high-performance parallel inference scheme. The high-level synthesis technique is adopted to design the ASIC, and VHSIC hardware description language (VHDL) is used to model it at the behavior domain.

UR - http://www.scopus.com/inward/record.url?scp=85065846468&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85065846468&partnerID=8YFLogxK

U2 - 10.1109/ASIC.1992.270195

DO - 10.1109/ASIC.1992.270195

M3 - Conference contribution

AN - SCOPUS:85065846468

T3 - Proceedings of International Conference on ASIC

SP - 577

EP - 580

BT - Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992

PB - IEEE Computer Society

T2 - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992

Y2 - 21 September 1992 through 25 September 1992

ER -

A fuzzy neural network chip based on systolic array architecture

Abstract

Publication series

Conference

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this