A fuzzy neural network chip based on systolic array architecture

Jiahn Jung Chen, Yau-Hwang Kuo, Cheng I. Kao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A neural network model using a fuzzy classification concept, called FNN, is proposed. The design of an ASIC that implements that FNN model is presented. The chip architecture is based on a one-dimensional systolic array architecture, which provides a low-cost and high-performance parallel inference scheme. The high-level synthesis technique is adopted to design the ASIC, and VHSIC hardware description language (VHDL) is used to model it at the behavior domain.

Original languageEnglish
Title of host publicationProceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
PublisherIEEE Computer Society
Pages577-580
Number of pages4
ISBN (Electronic)0780307682
DOIs
Publication statusPublished - 1992 Jan 1
Event5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 - Rochester, United States
Duration: 1992 Sep 211992 Sep 25

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Conference

Conference5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
CountryUnited States
CityRochester
Period92-09-2192-09-25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Chen, J. J., Kuo, Y-H., & Kao, C. I. (1992). A fuzzy neural network chip based on systolic array architecture. In Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 (pp. 577-580). [270195] (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASIC.1992.270195