A gate zero-bias 2W PHEMT power amplifier operating at 3.5 GHz

C. K. Chu; H. K. Huang; H. Z. Liu; C. H. Lin; M. P. Houng; Y. H. Wang; C. H. Chang; C. L. Wu; C. S. Chang

doi:10.1109/EDSSC.2005.1635243

A gate zero-bias 2W PHEMT power amplifier operating at 3.5 GHz

C. K. Chu
, H. K. Huang
, H. Z. Liu
, C. H. Lin
, M. P. Houng
, Y. H. Wang
, C. H. Chang
, C. L. Wu
, C. S. Chang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A single supply 2W MMIC power amplifier, operating between 3.3GHz and 3.8GHz by implementing AlGaAs/InGaAs/GaAs PHEMT for the applications of WiMax, is demonstrated. Using the gate zero-bias configuration, i.e., V_GS=0 and I_Dss, one can use only one single bias instead of dual bias in the depletion mode PHEMTs. This two-stage amplifier is designed by using a zero gate bias configuration i.e., V_GS=0 and at saturated drain current I_DSs, for class A power amplifier operation. The two-stage MMIC amplifier possesses the characteristics of 25.9dB small-signal gain and 34.0dBm 1-dB gain compression power. Moreover, with a single carrier output power level of 21dBm, very high linearity with a 47dBm third-order intercept point operating at 3.5GHz is also achieved.

Original language	English
Title of host publication	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	211-214
Number of pages	4
ISBN (Print)	0780393392, 9780780393394
DOIs	https://doi.org/10.1109/EDSSC.2005.1635243
Publication status	Published - 2005 Jan 1
Event	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC - Howloon, Hong Kong Duration: 2005 Dec 19 → 2005 Dec 21

Publication series

Name	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Other

Other	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Country/Territory	Hong Kong
City	Howloon
Period	05-12-19 → 05-12-21

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/EDSSC.2005.1635243

Cite this

Chu, C. K., Huang, H. K., Liu, H. Z., Lin, C. H., Houng, M. P., Wang, Y. H., Chang, C. H., Wu, C. L., & Chang, C. S. (2005). A gate zero-bias 2W PHEMT power amplifier operating at 3.5 GHz. In 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC (pp. 211-214). Article 1635243 (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2005.1635243

@inproceedings{b5c598026c004857b14ec45c964ae56f,

title = "A gate zero-bias 2W PHEMT power amplifier operating at 3.5 GHz",

abstract = "A single supply 2W MMIC power amplifier, operating between 3.3GHz and 3.8GHz by implementing AlGaAs/InGaAs/GaAs PHEMT for the applications of WiMax, is demonstrated. Using the gate zero-bias configuration, i.e., VGS=0 and IDss, one can use only one single bias instead of dual bias in the depletion mode PHEMTs. This two-stage amplifier is designed by using a zero gate bias configuration i.e., VGS=0 and at saturated drain current IDSs, for class A power amplifier operation. The two-stage MMIC amplifier possesses the characteristics of 25.9dB small-signal gain and 34.0dBm 1-dB gain compression power. Moreover, with a single carrier output power level of 21dBm, very high linearity with a 47dBm third-order intercept point operating at 3.5GHz is also achieved.",

author = "Chu, \{C. K.\} and Huang, \{H. K.\} and Liu, \{H. Z.\} and Lin, \{C. H.\} and Houng, \{M. P.\} and Wang, \{Y. H.\} and Chang, \{C. H.\} and Wu, \{C. L.\} and Chang, \{C. S.\}",

year = "2005",

month = jan,

day = "1",

doi = "10.1109/EDSSC.2005.1635243",

language = "English",

isbn = "0780393392",

series = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "211--214",

booktitle = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC",

address = "United States",

note = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC ; Conference date: 19-12-2005 Through 21-12-2005",

}

Chu, CK, Huang, HK, Liu, HZ, Lin, CH, Houng, MP, Wang, YH, Chang, CH, Wu, CL & Chang, CS 2005, A gate zero-bias 2W PHEMT power amplifier operating at 3.5 GHz. in 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC., 1635243, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Institute of Electrical and Electronics Engineers Inc., pp. 211-214, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Howloon, Hong Kong, 05-12-19. https://doi.org/10.1109/EDSSC.2005.1635243

A gate zero-bias 2W PHEMT power amplifier operating at 3.5 GHz. / Chu, C. K.; Huang, H. K.; Liu, H. Z. et al.
2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. Institute of Electrical and Electronics Engineers Inc., 2005. p. 211-214 1635243 (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A gate zero-bias 2W PHEMT power amplifier operating at 3.5 GHz

AU - Chu, C. K.

AU - Huang, H. K.

AU - Liu, H. Z.

AU - Lin, C. H.

AU - Houng, M. P.

AU - Wang, Y. H.

AU - Chang, C. H.

AU - Wu, C. L.

AU - Chang, C. S.

PY - 2005/1/1

Y1 - 2005/1/1

N2 - A single supply 2W MMIC power amplifier, operating between 3.3GHz and 3.8GHz by implementing AlGaAs/InGaAs/GaAs PHEMT for the applications of WiMax, is demonstrated. Using the gate zero-bias configuration, i.e., VGS=0 and IDss, one can use only one single bias instead of dual bias in the depletion mode PHEMTs. This two-stage amplifier is designed by using a zero gate bias configuration i.e., VGS=0 and at saturated drain current IDSs, for class A power amplifier operation. The two-stage MMIC amplifier possesses the characteristics of 25.9dB small-signal gain and 34.0dBm 1-dB gain compression power. Moreover, with a single carrier output power level of 21dBm, very high linearity with a 47dBm third-order intercept point operating at 3.5GHz is also achieved.

AB - A single supply 2W MMIC power amplifier, operating between 3.3GHz and 3.8GHz by implementing AlGaAs/InGaAs/GaAs PHEMT for the applications of WiMax, is demonstrated. Using the gate zero-bias configuration, i.e., VGS=0 and IDss, one can use only one single bias instead of dual bias in the depletion mode PHEMTs. This two-stage amplifier is designed by using a zero gate bias configuration i.e., VGS=0 and at saturated drain current IDSs, for class A power amplifier operation. The two-stage MMIC amplifier possesses the characteristics of 25.9dB small-signal gain and 34.0dBm 1-dB gain compression power. Moreover, with a single carrier output power level of 21dBm, very high linearity with a 47dBm third-order intercept point operating at 3.5GHz is also achieved.

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U2 - 10.1109/EDSSC.2005.1635243

DO - 10.1109/EDSSC.2005.1635243

M3 - Conference contribution

SN - 0780393392

SN - 9780780393394

T3 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

SP - 211

EP - 214

BT - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Y2 - 19 December 2005 through 21 December 2005

ER -

Chu CK, Huang HK, Liu HZ, Lin CH, Houng MP, Wang YH et al. A gate zero-bias 2W PHEMT power amplifier operating at 3.5 GHz. In 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. Institute of Electrical and Electronics Engineers Inc. 2005. p. 211-214. 1635243. (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC). doi: 10.1109/EDSSC.2005.1635243

A gate zero-bias 2W PHEMT power amplifier operating at 3.5 GHz

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