A GBAS receiver prototype based on FPGA for integrity monitoring test-bed

The Integrity Monitoring Test-bed (IMT) project is aimed to facilitate the implementation and operation of the Ground Based Augmentation System (GBAS) ground facility prototype in the Taipei Flight Information Region (FIR). The first goal of this project is to assess the effects on navigation performance due to various parameter changes in the algorithms of both the GBAS master station and reference stations, and the second goal is to evaluate the impacts on navigation performance from the changes in the GBAS user algorithms. This involves developing a GBAS receiver which completes trade-off studies to assess the performance of various architectures for both the GBAS ground facility and user avionics. In order to evaluate the performance of the IMT in the Taipei FIR, a dedicated GBAS receiver prototype as the user segment is therefore required. Accordingly, this study presents a real-time GBAS receiver prototype based on field-programmable gate array (FPGA) technology. Unlike a conventional hardware-based receiver, the FPGA implementation allows the GBAS user algorithms to be modified. The performance of these algorithms is compared to that of the standard GBAS user algorithms defined in RTCA DO-253D (GBAS minimum operational performance standards). Finally, several field tests at Kaohsiung International Airport, Taiwan (ICAO code: RCKH) are conducted to tune and verify the algorithms of the proposed GBAS receiver prototype under various scenarios. The receiver prototype is used to assess the relative performance benefits for various architectures of the IMT reference stations and master station. Furthermore, the Stanford chart is implemented into the proposed GBAS receiver prototype as the criteria to examine the accuracy, availability, and integrity of the developed IMT.