A graph representation for programmable logic arrays to facilitate testing and logic design

Jing Jou Tang, Kuen Jong Lee, Bin Da Liu

Research output: Contribution to journalArticlepeer-review

Abstract

In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLA's). The signal lines and devices of a PLA are represented as the edges and vertices of a directed graph, respectively. Through this graph model, most realistic PLA faults, including cross-point, stuck-at, break, and bridging faults, can be modeled and classified, and the maximal diagnosis resolution of a PLA can be determined. Moreover, the model can be easily transformed into a gate-level model. Hence, the work of automatic test-pattern generation for a PLA and for other random logic can be done simultaneously. We also show that this representation can be extended to some logic design techniques such as logic minimization, folding, and decomposition for PLA's. Thus, this graph model can unify the data structure and operations required in PLA design and test.

Original languageEnglish
Pages (from-to)1030-1043
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume17
Issue number10
DOIs
Publication statusPublished - 1998 Dec 1

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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