A gm/ID-based synthesis tool for pipelined analog to digital converters

Ya Ting Shyu, Cheng Wu Lin, Jin Fu Lin, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a circuit-level synthesis tool for pipelined ADCs by consulting the circuit-design experience. A top-down systematic design procedure for a conventional pipelined ADC is summarized. In order to decrease the design period for analog circuit sizing, a design automation methodology based on gm/ID concept is manipulated in the synthesis process. With the proposed design automation flow for pipelined ADCs, the developed synthesis tool can produce satisfactory circuit performance within reasonable simulation time.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages299-302
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
Duration: 2009 Apr 282009 Apr 30

Publication series

Name2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
CountryTaiwan
CityHsinchu
Period09-04-2809-04-30

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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