A hardware design approach for merge-sorting network

C. Y. Huang, G. J. Yu, Bin-Da Liu

Research output: Contribution to journalConference article

Abstract

In this paper, a hardware design methodology for merge-sorting networks, which uses a fixed size Batcher's sorting network, a data memory module and a memory addressing controller, is proposed. In this method, only by adjusting the data flow Of the memory addressing controller, the amount of sorting data can be extended easily. Particularly, the adjustment of data flow is quite regular. Therefore, the proposed method has the following merits: low complexity of parallel sorting networks, low hardware fabrication cost, high extensibility, high regularity and no extra data memory space needed. For verifying the proposed approach, a 128-item merge-sorting network has been designed and simulated by Verilog VHDL.

Original languageEnglish
JournalMaterials Research Society Symposium - Proceedings
Volume626
Publication statusPublished - 2001 Jan 1
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 2000 Apr 242000 Apr 27

Fingerprint

classifying
Sorting
hardware
Hardware
Data storage equipment
Computer hardware description languages
controllers
adjusting
hardware description languages
Controllers
regularity
modules
methodology
costs
Fabrication
fabrication
Costs

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

Cite this

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abstract = "In this paper, a hardware design methodology for merge-sorting networks, which uses a fixed size Batcher's sorting network, a data memory module and a memory addressing controller, is proposed. In this method, only by adjusting the data flow Of the memory addressing controller, the amount of sorting data can be extended easily. Particularly, the adjustment of data flow is quite regular. Therefore, the proposed method has the following merits: low complexity of parallel sorting networks, low hardware fabrication cost, high extensibility, high regularity and no extra data memory space needed. For verifying the proposed approach, a 128-item merge-sorting network has been designed and simulated by Verilog VHDL.",
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A hardware design approach for merge-sorting network. / Huang, C. Y.; Yu, G. J.; Liu, Bin-Da.

In: Materials Research Society Symposium - Proceedings, Vol. 626, 01.01.2001.

Research output: Contribution to journalConference article

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AU - Liu, Bin-Da

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AB - In this paper, a hardware design methodology for merge-sorting networks, which uses a fixed size Batcher's sorting network, a data memory module and a memory addressing controller, is proposed. In this method, only by adjusting the data flow Of the memory addressing controller, the amount of sorting data can be extended easily. Particularly, the adjustment of data flow is quite regular. Therefore, the proposed method has the following merits: low complexity of parallel sorting networks, low hardware fabrication cost, high extensibility, high regularity and no extra data memory space needed. For verifying the proposed approach, a 128-item merge-sorting network has been designed and simulated by Verilog VHDL.

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