Abstract
In this paper, a hardware design methodology for merge-sorting networks, which uses a fixed size Batcher's sorting network, a data memory module and a memory addressing controller, is proposed. In this method, only by adjusting the data flow Of the memory addressing controller, the amount of sorting data can be extended easily. Particularly, the adjustment of data flow is quite regular. Therefore, the proposed method has the following merits: low complexity of parallel sorting networks, low hardware fabrication cost, high extensibility, high regularity and no extra data memory space needed. For verifying the proposed approach, a 128-item merge-sorting network has been designed and simulated by Verilog VHDL.
| Original language | English |
|---|---|
| Journal | Materials Research Society Symposium - Proceedings |
| Volume | 626 |
| Publication status | Published - 2001 Jan 1 |
| Event | Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States Duration: 2000 Apr 24 → 2000 Apr 27 |
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All Science Journal Classification (ASJC) codes
- Materials Science(all)
- Condensed Matter Physics
- Mechanics of Materials
- Mechanical Engineering
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A hardware design approach for merge-sorting network. / Huang, C. Y.; Yu, G. J.; Liu, Bin-Da.
In: Materials Research Society Symposium - Proceedings, Vol. 626, 01.01.2001.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - A hardware design approach for merge-sorting network
AU - Huang, C. Y.
AU - Yu, G. J.
AU - Liu, Bin-Da
PY - 2001/1/1
Y1 - 2001/1/1
N2 - In this paper, a hardware design methodology for merge-sorting networks, which uses a fixed size Batcher's sorting network, a data memory module and a memory addressing controller, is proposed. In this method, only by adjusting the data flow Of the memory addressing controller, the amount of sorting data can be extended easily. Particularly, the adjustment of data flow is quite regular. Therefore, the proposed method has the following merits: low complexity of parallel sorting networks, low hardware fabrication cost, high extensibility, high regularity and no extra data memory space needed. For verifying the proposed approach, a 128-item merge-sorting network has been designed and simulated by Verilog VHDL.
AB - In this paper, a hardware design methodology for merge-sorting networks, which uses a fixed size Batcher's sorting network, a data memory module and a memory addressing controller, is proposed. In this method, only by adjusting the data flow Of the memory addressing controller, the amount of sorting data can be extended easily. Particularly, the adjustment of data flow is quite regular. Therefore, the proposed method has the following merits: low complexity of parallel sorting networks, low hardware fabrication cost, high extensibility, high regularity and no extra data memory space needed. For verifying the proposed approach, a 128-item merge-sorting network has been designed and simulated by Verilog VHDL.
UR - http://www.scopus.com/inward/record.url?scp=0035026856&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0035026856&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0035026856
VL - 626
JO - Materials Research Society Symposium - Proceedings
JF - Materials Research Society Symposium - Proceedings
SN - 0272-9172
ER -