A hardware design approach for merge-sorting network

C. Y. Huang, G. J. Yu, B. D. Liu

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)


In this paper, a hardware design methodology for merge-sorting networks, which uses a fixed size Batcher's sorting network, a data memory module and a memory addressing controller, is proposed. In this method, only by adjusting the data flow Of the memory addressing controller, the amount of sorting data can be extended easily. Particularly, the adjustment of data flow is quite regular. Therefore, the proposed method has the following merits: low complexity of parallel sorting networks, low hardware fabrication cost, high extensibility, high regularity and no extra data memory space needed. For verifying the proposed approach, a 128-item merge-sorting network has been designed and simulated by Verilog VHDL.

Original languageEnglish
Pages (from-to)IV534-IV537
JournalMaterials Research Society Symposium - Proceedings
Publication statusPublished - 2001
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 2000 Apr 242000 Apr 27

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering


Dive into the research topics of 'A hardware design approach for merge-sorting network'. Together they form a unique fingerprint.

Cite this