A key aspect of an IP core's marketability is its ability to be easily integrated across a wide variety of interfaces. In this paper, we propose an efficient hierarchical interface design methodology and models so that a designer can quickly design an IP core's interface, which can be easily integrated into any interface/bus architecture. The proposed methodology and models have been applied to design an MP3 decoder with different interfaces: an ISA bus interface and a PCI bus interface. The results demonstrate that the methodology and models result in easy IP integration and only a little performance overhead.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2002|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering