A hierarchical interface design methodology and models for SOC IP integration

Jer-Min Jou, Shiann Rong Kuang, Kuang Ming Wu

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A key aspect of an IP core's marketability is its ability to be easily integrated across a wide variety of interfaces. In this paper, we propose an efficient hierarchical interface design methodology and models so that a designer can quickly design an IP core's interface, which can be easily integrated into any interface/bus architecture. The proposed methodology and models have been applied to design an MP3 decoder with different interfaces: an ISA bus interface and a PCI bus interface. The results demonstrate that the methodology and models result in easy IP integration and only a little performance overhead.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
Publication statusPublished - 2002

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Intellectual property core

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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A hierarchical interface design methodology and models for SOC IP integration. / Jou, Jer-Min; Kuang, Shiann Rong; Wu, Kuang Ming.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 2002.

Research output: Contribution to journalArticle

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