System-on-a-chip (SOC) design based on IP cores has become the trend of IC design. The test problem previously unresolved becomes even more difficult in the SOC era. A test standard called P1500 is being developed by an IEEE Working Group with the aim to reduce the difficulty of the SOC test problem. In this paper, we propose a novel SOC test architecture that is compatible with the developing IEEE P1500 standard. Our architecture can also support the well-accepted boundary scan architecture. In addition, it provides a true control mechanism that facilitates the hierarchical test access for deeply-embedded cores in a plug-and-play manner.
|Number of pages||9|
|Journal||Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an|
|Publication status||Published - 2001 Nov 1|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering