A hierarchical test control architecture for SOC design

Kuen-Jong Lee, C. I. Huang

Research output: Contribution to journalArticle

Abstract

System-on-a-chip (SOC) design based on IP cores has become the trend of IC design. The test problem previously unresolved becomes even more difficult in the SOC era. A test standard called P1500 is being developed by an IEEE Working Group with the aim to reduce the difficulty of the SOC test problem. In this paper, we propose a novel SOC test architecture that is compatible with the developing IEEE P1500 standard. Our architecture can also support the well-accepted boundary scan architecture. In addition, it provides a true control mechanism that facilitates the hierarchical test access for deeply-embedded cores in a plug-and-play manner.

Original languageEnglish
Pages (from-to)355-363
Number of pages9
JournalJournal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an
Volume8
Issue number4
Publication statusPublished - 2001 Nov 1

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Integrated circuit design
Intellectual property core

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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