A high-density SRAM design technique using silicon nanowire FETs

Yi Bo Liao; Meng Hsueh Chiang; Keunwoo Kim; Wei Chou Hsu

doi:10.1109/ISDRS.2011.6135407

A high-density SRAM design technique using silicon nanowire FETs

Yi Bo Liao, Meng Hsueh Chiang, Keunwoo Kim, Wei Chou Hsu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A new all-single-wire 6T-SRAM technique using junctionless nanowire FETs is proposed. The quantization-free design shows a great advantage in Si-nanowire-based SRAM cells. TCAD-simulated results show that the proposed single-wire SRAM can improve Read stability, and it can save about one third of the area as compared with multi-wire design while it is compatible with conventional processing.

Original language	English
Title of host publication	2011 International Semiconductor Device Research Symposium, ISDRS 2011
DOIs	https://doi.org/10.1109/ISDRS.2011.6135407
Publication status	Published - 2011 Dec 1
Event	2011 International Semiconductor Device Research Symposium, ISDRS 2011 - College Park, MD, United States Duration: 2011 Dec 7 → 2011 Dec 9

Publication series

Name	2011 International Semiconductor Device Research Symposium, ISDRS 2011

Other

Other	2011 International Semiconductor Device Research Symposium, ISDRS 2011
Country/Territory	United States
City	College Park, MD
Period	11-12-07 → 11-12-09

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISDRS.2011.6135407

Cite this

@inproceedings{b03f9c4fd3674549ba813bd4726ed533,

title = "A high-density SRAM design technique using silicon nanowire FETs",

abstract = "A new all-single-wire 6T-SRAM technique using junctionless nanowire FETs is proposed. The quantization-free design shows a great advantage in Si-nanowire-based SRAM cells. TCAD-simulated results show that the proposed single-wire SRAM can improve Read stability, and it can save about one third of the area as compared with multi-wire design while it is compatible with conventional processing.",

author = "Liao, {Yi Bo} and Chiang, {Meng Hsueh} and Keunwoo Kim and Hsu, {Wei Chou}",

year = "2011",

month = dec,

day = "1",

doi = "10.1109/ISDRS.2011.6135407",

language = "English",

isbn = "9781457717550",

series = "2011 International Semiconductor Device Research Symposium, ISDRS 2011",

booktitle = "2011 International Semiconductor Device Research Symposium, ISDRS 2011",

note = "2011 International Semiconductor Device Research Symposium, ISDRS 2011 ; Conference date: 07-12-2011 Through 09-12-2011",

}

Liao, YB, Chiang, MH, Kim, K & Hsu, WC 2011, A high-density SRAM design technique using silicon nanowire FETs. in 2011 International Semiconductor Device Research Symposium, ISDRS 2011., 6135407, 2011 International Semiconductor Device Research Symposium, ISDRS 2011, 2011 International Semiconductor Device Research Symposium, ISDRS 2011, College Park, MD, United States, 11-12-07. https://doi.org/10.1109/ISDRS.2011.6135407

TY - GEN

T1 - A high-density SRAM design technique using silicon nanowire FETs

AU - Liao, Yi Bo

AU - Chiang, Meng Hsueh

AU - Kim, Keunwoo

AU - Hsu, Wei Chou

PY - 2011/12/1

Y1 - 2011/12/1

N2 - A new all-single-wire 6T-SRAM technique using junctionless nanowire FETs is proposed. The quantization-free design shows a great advantage in Si-nanowire-based SRAM cells. TCAD-simulated results show that the proposed single-wire SRAM can improve Read stability, and it can save about one third of the area as compared with multi-wire design while it is compatible with conventional processing.

AB - A new all-single-wire 6T-SRAM technique using junctionless nanowire FETs is proposed. The quantization-free design shows a great advantage in Si-nanowire-based SRAM cells. TCAD-simulated results show that the proposed single-wire SRAM can improve Read stability, and it can save about one third of the area as compared with multi-wire design while it is compatible with conventional processing.

UR - http://www.scopus.com/inward/record.url?scp=84863150001&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84863150001&partnerID=8YFLogxK

U2 - 10.1109/ISDRS.2011.6135407

DO - 10.1109/ISDRS.2011.6135407

M3 - Conference contribution

AN - SCOPUS:84863150001

SN - 9781457717550

T3 - 2011 International Semiconductor Device Research Symposium, ISDRS 2011

BT - 2011 International Semiconductor Device Research Symposium, ISDRS 2011

T2 - 2011 International Semiconductor Device Research Symposium, ISDRS 2011

Y2 - 7 December 2011 through 9 December 2011

ER -

A high-density SRAM design technique using silicon nanowire FETs

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this