A high gain, low noise wlan receiver for dual if double downconversion application in 90-nm RF CMOS

Chieh Pin Chang, Jian An Hou, Jionguang Su, Ja Hao Chen, Chih Wei Chen, Tsyr Shyang Liou, Shyh Chyi Wong, Yeong-Her Wang

Research output: Contribution to journalArticle

Abstract

A high power gain, low noise WLAN receiver, using a 158 GHz f T 90-nm RF CMOS technology for dual IF double downconversion system-in-package application is demonstrated. The proposed circuit could improve the design flexibility of back-end stages due to its high power gain and low noise performances. The LNA and Mixer are biased at 1 V with 12.9 mA and 1.8 V with 5.5 mA, respectively. The proposed circuit delivers the double-sideband noise figure of 2.68 dB, conversion gain of 36.24 dB, IIP3 of -25 dBm, IIP2 of 21.1 dBm, and LO-IF isolation of -56.2 dB under the 1 dBm LO power, while maintaining the RF port and IF port return losses below -12.9 and -18.7 dB, respectively.

Original languageEnglish
Pages (from-to)2422-2425
Number of pages4
JournalMicrowave and Optical Technology Letters
Volume49
Issue number10
DOIs
Publication statusPublished - 2007 Oct 1

Fingerprint

power gain
high gain
low noise
CMOS
receivers
Networks (circuits)
Noise figure
Wireless local area networks (WLAN)
sidebands
isolation
flexibility
System-in-package

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Chang, Chieh Pin ; Hou, Jian An ; Su, Jionguang ; Chen, Ja Hao ; Chen, Chih Wei ; Liou, Tsyr Shyang ; Wong, Shyh Chyi ; Wang, Yeong-Her. / A high gain, low noise wlan receiver for dual if double downconversion application in 90-nm RF CMOS. In: Microwave and Optical Technology Letters. 2007 ; Vol. 49, No. 10. pp. 2422-2425.
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abstract = "A high power gain, low noise WLAN receiver, using a 158 GHz f T 90-nm RF CMOS technology for dual IF double downconversion system-in-package application is demonstrated. The proposed circuit could improve the design flexibility of back-end stages due to its high power gain and low noise performances. The LNA and Mixer are biased at 1 V with 12.9 mA and 1.8 V with 5.5 mA, respectively. The proposed circuit delivers the double-sideband noise figure of 2.68 dB, conversion gain of 36.24 dB, IIP3 of -25 dBm, IIP2 of 21.1 dBm, and LO-IF isolation of -56.2 dB under the 1 dBm LO power, while maintaining the RF port and IF port return losses below -12.9 and -18.7 dB, respectively.",
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A high gain, low noise wlan receiver for dual if double downconversion application in 90-nm RF CMOS. / Chang, Chieh Pin; Hou, Jian An; Su, Jionguang; Chen, Ja Hao; Chen, Chih Wei; Liou, Tsyr Shyang; Wong, Shyh Chyi; Wang, Yeong-Her.

In: Microwave and Optical Technology Letters, Vol. 49, No. 10, 01.10.2007, p. 2422-2425.

Research output: Contribution to journalArticle

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