TY - GEN
T1 - A high performance and low cost entropy encoder for H.264 AVC baseline entropy coding
AU - Huang, Feng Min
AU - Lei, Sheau Fang
PY - 2008
Y1 - 2008
N2 - This paper presents a high performance and low cost architecture for H.264/AVC baseline profile entropy encoder. In the proposed design, an efficient method is used to design CAVLC to reduce the hardware cost. The regularity of nC calculation allows the architecture in reducing area. With the synthesis constraint of 100Mhz clock, the logic gate count of the proposed design is 16K gates based on a 0.18 μm TSMC cell library. The power consumption of the proposed hardware is 2.5mW at 27Mhz and 1.8V. The implemented architecture can achieve the real-time processing requirement for HD 1080 format video sequences.
AB - This paper presents a high performance and low cost architecture for H.264/AVC baseline profile entropy encoder. In the proposed design, an efficient method is used to design CAVLC to reduce the hardware cost. The regularity of nC calculation allows the architecture in reducing area. With the synthesis constraint of 100Mhz clock, the logic gate count of the proposed design is 16K gates based on a 0.18 μm TSMC cell library. The power consumption of the proposed hardware is 2.5mW at 27Mhz and 1.8V. The implemented architecture can achieve the real-time processing requirement for HD 1080 format video sequences.
UR - https://www.scopus.com/pages/publications/58149159306
UR - https://www.scopus.com/pages/publications/58149159306#tab=citedBy
U2 - 10.1109/ICCCAS.2008.4657863
DO - 10.1109/ICCCAS.2008.4657863
M3 - Conference contribution
AN - SCOPUS:58149159306
SN - 9781424420636
T3 - 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
SP - 675
EP - 678
BT - 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
T2 - 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
Y2 - 25 May 2008 through 27 May 2008
ER -