TY - JOUR
T1 - A high-performance unified-field reconfigurable cryptographic processor
AU - Chen, Jun Hong
AU - Shieh, Ming Der
AU - Lin, Wen Ching
N1 - Funding Information:
Manuscript received September 01, 2008; revised January 18, 2009; accepted March 18, 2009. First published November 10, 2009; current version published July 23, 2010. This work was supported in part by the National Science Council of R.O.C. under Contract NSC 96-2220-E-006-008.
PY - 2010/8
Y1 - 2010/8
N2 - With rapid increases in communication and network applications, cryptography has become a crucial issue to ensure the security of transmitted data. In this paper, we propose a microcode-based architecture with a novel reconfigurable datapath which can perform either prime field GF(p) operations or binary extension field GF(2m) operations for arbitrary prime numbers, irreducible polynomials, and precision. Using these field arithmetic units, users are capable of programming cryptographic algorithms in microcode sequences for full compliance with a majority of public-key cryptographic algorithms such as RivestShamirAdleman (RSA) and elliptic curve cryptosystems. An algorithmic optimization or refinement can thus be made at a higher level based on the reconfigurable datapath. Experimental results show that the developed processor has full cryptography algorithm flexibility, high hardware utilization, and high performance.
AB - With rapid increases in communication and network applications, cryptography has become a crucial issue to ensure the security of transmitted data. In this paper, we propose a microcode-based architecture with a novel reconfigurable datapath which can perform either prime field GF(p) operations or binary extension field GF(2m) operations for arbitrary prime numbers, irreducible polynomials, and precision. Using these field arithmetic units, users are capable of programming cryptographic algorithms in microcode sequences for full compliance with a majority of public-key cryptographic algorithms such as RivestShamirAdleman (RSA) and elliptic curve cryptosystems. An algorithmic optimization or refinement can thus be made at a higher level based on the reconfigurable datapath. Experimental results show that the developed processor has full cryptography algorithm flexibility, high hardware utilization, and high performance.
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U2 - 10.1109/TVLSI.2009.2020397
DO - 10.1109/TVLSI.2009.2020397
M3 - Article
AN - SCOPUS:77955172157
SN - 1063-8210
VL - 18
SP - 1145
EP - 1158
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 8
M1 - 5325648
ER -