A high-speed and decentralized arbiter design for NoC

Yun Lung Lee, Jer Min Jou, Yen Yu Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Abstract

As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and Decentralized Round-robin Arbiter (HDRA) is presented. Unlike the conventional round-robin arbiters, the HDRA design, based on a de-centralized structure, is fast with only O(log4N) in critical path delay, area-efficient, and fair. The design results of it show that the arbitration performance of the HDRA is best compared with all existing arbiters, and still has smaller area cost. This new arbiter is being applied for a patent of the ROC (application No.: 0971xxxxx).

Original languageEnglish
Title of host publication2009 IEEE/ACS International Conference on Computer Systems and Applications, AICCSA 2009
Pages350-353
Number of pages4
DOIs
Publication statusPublished - 2009 Oct 19
Event7th IEEE/ACS International Conference on Computer Systems and Applications, AICCSA-2009 - Rabat, Morocco
Duration: 2009 May 102009 May 13

Publication series

Name2009 IEEE/ACS International Conference on Computer Systems and Applications, AICCSA 2009

Other

Other7th IEEE/ACS International Conference on Computer Systems and Applications, AICCSA-2009
Country/TerritoryMorocco
CityRabat
Period09-05-1009-05-13

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Computer Science Applications
  • Electrical and Electronic Engineering

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