A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique

Jin Fu Lin, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In this paper, a pipelined analog-to-digital converter (ADC) which employs a modified time-shifted correlated double sampling (CDS) technique is proposed. The conventional time-shifted CDS technique can significantly reduce the errors due to the finite gain of the operational amplifier (op-amp) without compromising the conversion speed. However, it needs a high-linearity op-amp to realize the front-end sample-and-hold (SHA) such that the sampled signal without being distorted too much. In order to relax the highlinearity requirement of the op-amp, a new type of SHA circuit is presented.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages5367-5370
Number of pages4
Publication statusPublished - 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 2006 May 212006 May 24

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period06-05-2106-05-24

Fingerprint

Operational amplifiers
Digital to analog conversion
Sampling
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Lin, J. F., & Chang, S-J. (2006). A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings (pp. 5367-5370). [1693846]
Lin, Jin Fu ; Chang, Soon-Jyh. / A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. pp. 5367-5370
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Lin, JF & Chang, S-J 2006, A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693846, pp. 5367-5370, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 06-05-21.

A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. / Lin, Jin Fu; Chang, Soon-Jyh.

ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 5367-5370 1693846.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lin JF, Chang S-J. A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 5367-5370. 1693846