A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique

Jin Fu Lin; Soon Jyh Chang

A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique

Jin Fu Lin, Soon Jyh Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

In this paper, a pipelined analog-to-digital converter (ADC) which employs a modified time-shifted correlated double sampling (CDS) technique is proposed. The conventional time-shifted CDS technique can significantly reduce the errors due to the finite gain of the operational amplifier (op-amp) without compromising the conversion speed. However, it needs a high-linearity op-amp to realize the front-end sample-and-hold (SHA) such that the sampled signal without being distorted too much. In order to relax the highlinearity requirement of the op-amp, a new type of SHA circuit is presented.

Original language	English
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	5367-5370
Number of pages	4
Publication status	Published - 2006
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 2006 May 21 → 2006 May 24

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/Territory	Greece
City	Kos
Period	06-05-21 → 06-05-24

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

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title = "A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique",

abstract = "In this paper, a pipelined analog-to-digital converter (ADC) which employs a modified time-shifted correlated double sampling (CDS) technique is proposed. The conventional time-shifted CDS technique can significantly reduce the errors due to the finite gain of the operational amplifier (op-amp) without compromising the conversion speed. However, it needs a high-linearity op-amp to realize the front-end sample-and-hold (SHA) such that the sampled signal without being distorted too much. In order to relax the highlinearity requirement of the op-amp, a new type of SHA circuit is presented.",

author = "Lin, {Jin Fu} and Chang, {Soon Jyh}",

year = "2006",

language = "English",

isbn = "0780393902",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "5367--5370",

booktitle = "ISCAS 2006",

note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",

}

Lin, JF & Chang, SJ 2006, A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693846, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 5367-5370, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 06-05-21.

A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. / Lin, Jin Fu; Chang, Soon Jyh.
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 5367-5370 1693846 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - In this paper, a pipelined analog-to-digital converter (ADC) which employs a modified time-shifted correlated double sampling (CDS) technique is proposed. The conventional time-shifted CDS technique can significantly reduce the errors due to the finite gain of the operational amplifier (op-amp) without compromising the conversion speed. However, it needs a high-linearity op-amp to realize the front-end sample-and-hold (SHA) such that the sampled signal without being distorted too much. In order to relax the highlinearity requirement of the op-amp, a new type of SHA circuit is presented.

AB - In this paper, a pipelined analog-to-digital converter (ADC) which employs a modified time-shifted correlated double sampling (CDS) technique is proposed. The conventional time-shifted CDS technique can significantly reduce the errors due to the finite gain of the operational amplifier (op-amp) without compromising the conversion speed. However, it needs a high-linearity op-amp to realize the front-end sample-and-hold (SHA) such that the sampled signal without being distorted too much. In order to relax the highlinearity requirement of the op-amp, a new type of SHA circuit is presented.

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M3 - Conference contribution

AN - SCOPUS:34547324226

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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BT - ISCAS 2006

T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems

Y2 - 21 May 2006 through 24 May 2006

ER -

A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique

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