A high-throughput low-cost AES cipher chip

Tsung Fu Lin; Chih Pin Su; Chih Tsun Huang; Cheng Wen Wu

doi:10.1109/APASIC.2002.1031538

A high-throughput low-cost AES cipher chip

Tsung Fu Lin, Chih Pin Su, Chih Tsun Huang, Cheng Wen Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

36 Citations (Scopus)

Abstract

We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 μm CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5 K gates.

Original language	English
Title of host publication	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	85-88
Number of pages	4
ISBN (Electronic)	0780373634, 9780780373631
DOIs	https://doi.org/10.1109/APASIC.2002.1031538
Publication status	Published - 2002 Jan 1
Event	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan Duration: 2002 Aug 6 → 2002 Aug 8

Publication series

Name	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Country/Territory	Taiwan
City	Taipei
Period	02-08-06 → 02-08-08

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/APASIC.2002.1031538

Cite this

Lin, T. F., Su, C. P., Huang, C. T., & Wu, C. W. (2002). A high-throughput low-cost AES cipher chip. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (pp. 85-88). Article 1031538 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031538

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abstract = "We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 μm CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5 K gates.",

author = "Lin, {Tsung Fu} and Su, {Chih Pin} and Huang, {Chih Tsun} and Wu, {Cheng Wen}",

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Lin, TF, Su, CP, Huang, CT & Wu, CW 2002, A high-throughput low-cost AES cipher chip. in 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings., 1031538, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 85-88, 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002, Taipei, Taiwan, 02-08-06. https://doi.org/10.1109/APASIC.2002.1031538

A high-throughput low-cost AES cipher chip. / Lin, Tsung Fu; Su, Chih Pin; Huang, Chih Tsun et al.
2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. p. 85-88 1031538 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 μm CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5 K gates.

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A high-throughput low-cost AES cipher chip

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