A highly efficient AES cipher chip

Chih Pin Su, Tsung Fu Lin, Chih Tsun Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)


We present an efficient hardware implementation of the AES (advanced encryption standard) algorithm, with key expansion capability. Instead of the widely used table-lookup implementation of the S-box, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64% and is easily pipelined to achieve high throughput rate. Using a typical 0.25 μm CMOS technology, the throughput rate is 2.977 Gbps for 128 bit keys, 2.510 Gbps for 192 bit keys, and 2.169 Gbps for 256 bit keys, with a 250 MHz clock. Testability of the design is also considered. The area of the core circuit is about 1,279×1,271 μm2.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)0780376595
Publication statusPublished - 2003 Jan 1
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 2003 Jan 212003 Jan 24

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC


OtherAsia and South Pacific Design Automation Conference, ASP-DAC 2003

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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