A hybrid BIST scheme for multiple heterogeneous embedded memories

Li Ming Denq, Cheng W. Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

It is common that an SOC contains hundreds or even thousands of heterogeneous embedded memories. Many of these embedded memories have wide data words, leading to high routing penalty from the BIST circuits. Previous BIST schemes solve the problem using serial interface, e.g., based on the IEEE 1500 architecture and novel scan approaches, to reduce the routing area overhead. However, serial approaches do not allow at-speed test and diagnosis, and are very slow. In this paper, we propose a hybrid BIST architecture that reduces the routing penalty, while allowing at-speed test and diagnosis of the memory cores. The test time is close to that of a typical parallel BIST method. Experimental results show that the proposed BIST can effectively reduce the area overhead.

Original languageEnglish
Title of host publicationProceedings of the 16th Asian Test Symposium, ATS 2007
Pages349-354
Number of pages6
DOIs
Publication statusPublished - 2007 Dec 1
Event16th Asian Test Symposium, ATS 2007 - Beijing, China
Duration: 2007 Oct 82007 Oct 11

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other16th Asian Test Symposium, ATS 2007
CountryChina
CityBeijing
Period07-10-0807-10-11

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Media Technology

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  • Cite this

    Denq, L. M., & Wu, C. W. (2007). A hybrid BIST scheme for multiple heterogeneous embedded memories. In Proceedings of the 16th Asian Test Symposium, ATS 2007 (pp. 349-354). [4388037] (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2007.4388037