A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

Yun Chao Yu, Chih Sheng Hou, Li Jung Chang, Jin Fu Li, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)


Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40∼70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.

Original languageEnglish
Title of host publicationProceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
Publication statusPublished - 2013 Aug 14
Event2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States
Duration: 2013 Apr 292013 May 1

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference2013 IEEE 31st VLSI Test Symposium, VTS 2013
Country/TerritoryUnited States
CityBerkeley, CA

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering


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