A hybrid LFSR design for low power applications

Linear feedback shift registers are commonly used in many fields, such as in built-in self-testing (BIST), compression, and communication. A parallel implementation of an n-stage LFSR using an n-phase clocking scheme has been proposed to reduce the data transitions during test and signal processes; however, due to the more complex clock generator, broadcasting input, and demultiplexing output, the power reduction of previous work is actually quite limited. This paper improves the power reduction by developing a novel low-power and cost-effective Johnson counter for the multiphase clock generator, as well as employing static logic gates to implement the output demultiplexer. To reduce the stages of the multiphase clock generator and the area of the demultiplexer, a hybrid LFSR design combining both single and multiple phase clocks has been developed. From our evaluation based on a transition model (taking into account the power dissipation due to the clock tree, the broadcasting input and the demultiplexing output, when n is greater than 28), our architecture has 40% more power reduction than the previous n-phase LFSR architecture, and up to 70% power reduction compared to a conventional LFSR.