A hybrid software-based self-testing methodology for embedded processor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)


Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test routine development or generation can base on deterministic and random methodology. The deterministic test methodology develops the test program for a pipeline processor using the information abstracted from its architecture model, RTL descriptions, and gate-level net-list for different types of processor circuits. The random test methodology tries to make the pseudo-exhaustive testing possible using random instructions or patterns. The proposed methodology improves coverage for structural faults using both deterministic and random development of the test code. Not only can the deterministic test program test lots of faults using very small code size, but also the random test program can help detect some of the faults that the deterministic test program is difficult to test. We demonstrated the feasibility of the proposed methodology by the achieved fault coverage, test program size, and testing cycle count on a complex pipeline processor core. Comparisons with previous work are also made. Experimental results show its potential as an effective method for practical use.

Original languageEnglish
Title of host publicationProceedings of the 23rd Annual ACM Symposium on Applied Computing, SAC'08
Number of pages7
Publication statusPublished - 2008 Dec 1
Event23rd Annual ACM Symposium on Applied Computing, SAC'08 - Fortaleza, Ceara, Brazil
Duration: 2008 Mar 162008 Mar 20

Publication series

NameProceedings of the ACM Symposium on Applied Computing


Other23rd Annual ACM Symposium on Applied Computing, SAC'08
CityFortaleza, Ceara

All Science Journal Classification (ASJC) codes

  • Software


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