A jitter characterizing BIST with pulse-amplifying technique

An Sheng Chao, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A built-in self-test (BIST) circuit for jitter measurement is proposed. The BIST circuit contains an improved cyclic time-to-digital converter (TDC) to achieve 6-ps resolution, and a pulse amplifier (PA) in front of the cyclic TDC to equivalently enhance timing resolution to 0.6 ps. The quantity of jitter is derived by analyzing the digital output codes of the BIST circuit. The input frequency range of the signal-under-test (SUT) is from 200 MHz to 2 GHz for 0.6-ps timing resolution, and from 100 Hz to 2 GHz for 6-ps timing resolution. In addition to the wide input frequency range and fine resolution, the proposed BIST reduces testi0ng time maximally by 95 % in comparison with the conventional BIST circuit based on component-invariant vernier delay line TDC. The presented BIST circuit occupies 0.6 0.336 mm2in a 0.18- uμm CMOS process.

Original languageEnglish
Title of host publicationProceedings of the 18th Asian Test Symposium, ATS 2009
Pages379-384
Number of pages6
DOIs
Publication statusPublished - 2009 Dec 1
Event18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan
Duration: 2009 Nov 232009 Nov 26

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other18th Asian Test Symposium, ATS 2009
Country/TerritoryTaiwan
CityTaichung
Period09-11-2309-11-26

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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