A joint project to develop a VLSI testing and design for testability course for universities in Taiwan

C.-L. Lee, J.-Y. Jou, C.-S. Lin, J.-E. Chen, K.-J. Lee, C.-C. Su, Cheng-Wen Wu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English
Title of host publication	International Conference on Engineering Education (ICEE)
Place of Publication	Chicago
Pages	43-53
Volume	II
Publication status	Published - 1997 Aug

Cite this

@inproceedings{a8a9a8d5f5d0456198aed72684f2a2e1,

title = "A joint project to develop a VLSI testing and design for testability course for universities in Taiwan",

author = "C.-L. Lee and J.-Y. Jou and C.-S. Lin and J.-E. Chen and K.-J. Lee and C.-C. Su and Cheng-Wen Wu",

year = "1997",

month = aug,

language = "English",

volume = "II",

pages = "43--53",

booktitle = "International Conference on Engineering Education (ICEE)",

}

TY - GEN

T1 - A joint project to develop a VLSI testing and design for testability course for universities in Taiwan

AU - Lee, C.-L.

AU - Jou, J.-Y.

AU - Lin, C.-S.

AU - Chen, J.-E.

AU - Lee, K.-J.

AU - Su, C.-C.

AU - Wu, Cheng-Wen

PY - 1997/8

Y1 - 1997/8

M3 - Conference contribution

VL - II

SP - 43

EP - 53

BT - International Conference on Engineering Education (ICEE)

CY - Chicago

ER -