TY - GEN
T1 - A light energy harvesting single-inductor dual-input dual-output converter for WSN
AU - Huang, Peng Chang
AU - Kuo, Tai Haur
PY - 2019/4
Y1 - 2019/4
N2 - A single-inductor dual-input dual-output (SIDIDO) converter is proposed for power management among photovoltaic (PV) module, storage element, and load in light energy harvesting systems. Low power maximum power point tracking (MPPT) and voltage regulation circuits are realized to harvest maximum power from a PV module and provide a regulated voltage for load. The chip including the SIDIDO converter and the control circuits are fabricated in 0.5μm CMOS process with 0.5mm2active area. The measured peak conversion efficiency is 93%, while the measured quiescent current is 1μA. Moreover, for wireless sensor node applications, an RF transceiver supplied by a light energy system with proposed IC is also measured.
AB - A single-inductor dual-input dual-output (SIDIDO) converter is proposed for power management among photovoltaic (PV) module, storage element, and load in light energy harvesting systems. Low power maximum power point tracking (MPPT) and voltage regulation circuits are realized to harvest maximum power from a PV module and provide a regulated voltage for load. The chip including the SIDIDO converter and the control circuits are fabricated in 0.5μm CMOS process with 0.5mm2active area. The measured peak conversion efficiency is 93%, while the measured quiescent current is 1μA. Moreover, for wireless sensor node applications, an RF transceiver supplied by a light energy system with proposed IC is also measured.
UR - http://www.scopus.com/inward/record.url?scp=85068599802&partnerID=8YFLogxK
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U2 - 10.1109/VLSI-DAT.2019.8742058
DO - 10.1109/VLSI-DAT.2019.8742058
M3 - Conference contribution
T3 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
BT - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Y2 - 22 April 2019 through 25 April 2019
ER -