A low-complexity and high-performance 2D look-up table for LDPC hardware implementation

Jung Chieh Chen, Po Hui Yang, Jenn Kaie Lain, Tzu Wen Chung

Research output: Contribution to journalArticlepeer-review

Abstract

In this paper, we propose a low-complexity, high-efficiency two-dimensional look-up table (2D LUT) for carrying out the sum-product algorithm in the decoding of low-density parity-check (LDPC) codes. Instead of employing adders for the core operation when updating check node messages, in the proposed scheme, the main term and correction factor of the core operation are successfully merged into a compact 2D LUT. Simulation results indicate that the proposed 2D LUT not only attains close-to-optimal bit error rate performance but also enjoys a low complexity advantage that is suitable for hardware implementation.

Original languageEnglish
Pages (from-to)2941-2944
Number of pages4
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE92-A
Issue number11
DOIs
Publication statusPublished - 2009 Nov

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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